_MASKED_BIT_DISABLE 887 drivers/gpu/drm/i915/gt/intel_engine_cs.c ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); _MASKED_BIT_DISABLE 2333 drivers/gpu/drm/i915/gt/intel_lrc.c ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); _MASKED_BIT_DISABLE 3211 drivers/gpu/drm/i915/gt/intel_lrc.c _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) | _MASKED_BIT_DISABLE 3215 drivers/gpu/drm/i915/gt/intel_lrc.c _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | _MASKED_BIT_DISABLE 485 drivers/gpu/drm/i915/gt/intel_reset.c _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); _MASKED_BIT_DISABLE 723 drivers/gpu/drm/i915/gt/intel_ringbuffer.c RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); _MASKED_BIT_DISABLE 901 drivers/gpu/drm/i915/gt/intel_ringbuffer.c _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); _MASKED_BIT_DISABLE 1674 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = _MASKED_BIT_DISABLE( _MASKED_BIT_DISABLE 2040 drivers/gpu/drm/i915/gt/intel_ringbuffer.c _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); _MASKED_BIT_DISABLE 184 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask)) _MASKED_BIT_DISABLE 1064 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING); _MASKED_BIT_DISABLE 483 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags)); _MASKED_BIT_DISABLE 1725 drivers/gpu/drm/i915/gvt/handlers.c || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { _MASKED_BIT_DISABLE 1788 drivers/gpu/drm/i915/gvt/handlers.c else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) _MASKED_BIT_DISABLE 395 drivers/gpu/drm/i915/intel_pm.c _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); _MASKED_BIT_DISABLE 406 drivers/gpu/drm/i915/intel_pm.c _MASKED_BIT_DISABLE(INSTPM_SELF_EN); _MASKED_BIT_DISABLE 8970 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); _MASKED_BIT_DISABLE 9038 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); _MASKED_BIT_DISABLE 9052 drivers/gpu/drm/i915/intel_pm.c _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); _MASKED_BIT_DISABLE 9365 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); _MASKED_BIT_DISABLE 9369 drivers/gpu/drm/i915/intel_pm.c _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); _MASKED_BIT_DISABLE 9417 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); _MASKED_BIT_DISABLE 9462 drivers/gpu/drm/i915/intel_pm.c _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); _MASKED_BIT_DISABLE 9509 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); _MASKED_BIT_DISABLE 9620 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); _MASKED_BIT_DISABLE 9641 drivers/gpu/drm/i915/intel_pm.c _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); _MASKED_BIT_DISABLE 9656 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); _MASKED_BIT_DISABLE 9671 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); _MASKED_BIT_DISABLE 9689 drivers/gpu/drm/i915/intel_pm.c _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); _MASKED_BIT_DISABLE 9959 drivers/gpu/drm/i915/intel_pm.c _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); _MASKED_BIT_DISABLE 90 drivers/gpu/drm/i915/intel_uncore.c #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)