_A1               125 arch/powerpc/xmon/spu-insns.h APUOP(M_BR,		RI16,	0x190,	"br",		_A1(A_R18),	00000,	BR)	/* BRel          IP<-IP+I16 */
_A1               127 arch/powerpc/xmon/spu-insns.h APUOP(M_BRA,		RI16,	0x180,	"bra",		_A1(A_S18),	00000,	BR)	/* BRAbs         IP<-I16 */
_A1               133 arch/powerpc/xmon/spu-insns.h APUOP(M_STOP2,		RR,	0x000,	"stop",		_A1(A_U14),	00000,	BR)	/* STOP          stop */
_A1               152 arch/powerpc/xmon/spu-insns.h APUOP(M_BI,		RR,	0x1a8,	"bi",		_A1(A_A),		00010,	BR)	/* BI            IP<-RA */
_A1               154 arch/powerpc/xmon/spu-insns.h APUOP(M_IRET,  		RR,	0x1aa,	"iret",	        _A1(A_A), 	00010,	BR)	/* IRET          IP<-SRR0 */
_A1               201 arch/powerpc/xmon/spu-insns.h APUOP(M_NOP,		RR,	0x201,	"nop",		_A1(A_T),		00000,	NOP)	/* XNOP          no_operation */
_A1               241 arch/powerpc/xmon/spu-insns.h APUOP(M_FSCRRD,		RR,	0x398,	"fscrrd",	_A1(A_T),		00002,	FPD)	/* FSCRRD        RT<-FP_status */
_A1               243 arch/powerpc/xmon/spu-insns.h APUOP(M_FSCRWR2,	RR,	0x3ba,	"fscrwr",	_A1(A_A),		00010,	FP7)	/* FSCRWR        FP_status<-RA */
_A1               359 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BID,		RR,	0x1a8,	0x20,	"bid",		_A1(A_A),		00010,	BR)	/* BI            IP<-RA */
_A1               360 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIE,		RR,	0x1a8,	0x10,	"bie",		_A1(A_A),		00010,	BR)	/* BI            IP<-RA */
_A1               363 arch/powerpc/xmon/spu-insns.h APUOPFB(M_IRETD,  	RR,	0x1aa,	0x20,	"iretd",	_A1(A_A), 	00010,	BR)	/* IRET          IP<-SRR0 */
_A1               365 arch/powerpc/xmon/spu-insns.h APUOPFB(M_IRETE,  	RR,	0x1aa,	0x10,	"irete",	_A1(A_A), 	00010,	BR)	/* IRET          IP<-SRR0 */
_A1               396 arch/powerpc/xmon/spu-insns.h #undef _A1