XX1_MASK         2630 arch/powerpc/xmon/ppc-opc.c #define XX1RB_MASK (XX1_MASK | RB_MASK)
XX1_MASK         4717 arch/powerpc/xmon/ppc-opc.c {"lxsiwzx",	X(31,12),	XX1_MASK,    PPCVSX2,	0,		{XT6, RA0, RB}},
XX1_MASK         4781 arch/powerpc/xmon/ppc-opc.c {"lxsiwax",	X(31,76),	XX1_MASK,    PPCVSX2,	0,		{XT6, RA0, RB}},
XX1_MASK         4911 arch/powerpc/xmon/ppc-opc.c {"stxsiwx",	X(31,140),	XX1_MASK,    PPCVSX2,	0,		{XS6, RA0, RB}},
XX1_MASK         5088 arch/powerpc/xmon/ppc-opc.c {"lxvx",	X(31,268),	XX1_MASK|1<<6, PPCVSX3,	0,		{XT6, RA0, RB}},
XX1_MASK         5089 arch/powerpc/xmon/ppc-opc.c {"lxvl",	X(31,269),	XX1_MASK,    PPCVSX3,	0,		{XT6, RA0, RB}},
XX1_MASK         5122 arch/powerpc/xmon/ppc-opc.c {"lxvll",	X(31,301),	XX1_MASK,    PPCVSX3,	0,		{XT6, RA0, RB}},
XX1_MASK         5190 arch/powerpc/xmon/ppc-opc.c {"lxvdsx",	X(31,332),	XX1_MASK,    PPCVSX,	0,		{XT6, RA0, RB}},
XX1_MASK         5413 arch/powerpc/xmon/ppc-opc.c {"lxvwsx",	X(31,364),	XX1_MASK,    PPCVSX3,	0,		{XT6, RA0, RB}},
XX1_MASK         5442 arch/powerpc/xmon/ppc-opc.c {"stxvx",	X(31,396),	XX1_MASK,    PPCVSX3,	0,		{XS6, RA0, RB}},
XX1_MASK         5443 arch/powerpc/xmon/ppc-opc.c {"stxvl",	X(31,397),	XX1_MASK,    PPCVSX3,	0,		{XS6, RA0, RB}},
XX1_MASK         5474 arch/powerpc/xmon/ppc-opc.c {"stxvll",	X(31,429),	XX1_MASK,    PPCVSX3,	0,		{XS6, RA0, RB}},
XX1_MASK         5480 arch/powerpc/xmon/ppc-opc.c {"mtvsrdd",	X(31,435),	XX1_MASK,    PPCVSX3,	0,		{XT6, RA0, RB}},
XX1_MASK         5774 arch/powerpc/xmon/ppc-opc.c {"lxsspx",	X(31,524),	XX1_MASK,    PPCVSX2,	0,		{XT6, RA0, RB}},
XX1_MASK         5838 arch/powerpc/xmon/ppc-opc.c {"lxsdx",	X(31,588),	XX1_MASK,    PPCVSX,	0,		{XT6, RA0, RB}},
XX1_MASK         5886 arch/powerpc/xmon/ppc-opc.c {"stxsspx",	X(31,652),	XX1_MASK,    PPCVSX2,	0,		{XS6, RA0, RB}},
XX1_MASK         5945 arch/powerpc/xmon/ppc-opc.c {"stxsdx",	X(31,716),	XX1_MASK,    PPCVSX,	0,		{XS6, RA0, RB}},
XX1_MASK         6034 arch/powerpc/xmon/ppc-opc.c {"lxvw4x",	X(31,780),	XX1_MASK,    PPCVSX,	0,		{XT6, RA0, RB}},
XX1_MASK         6035 arch/powerpc/xmon/ppc-opc.c {"lxsibzx",	X(31,781),	XX1_MASK,    PPCVSX3,	0,		{XT6, RA0, RB}},
XX1_MASK         6062 arch/powerpc/xmon/ppc-opc.c {"lxvh8x",	X(31,812),	XX1_MASK,    PPCVSX3,	0,		{XT6, RA0, RB}},
XX1_MASK         6063 arch/powerpc/xmon/ppc-opc.c {"lxsihzx",	X(31,813),	XX1_MASK,    PPCVSX3,	0,		{XT6, RA0, RB}},
XX1_MASK         6092 arch/powerpc/xmon/ppc-opc.c {"lxvd2x",	X(31,844),	XX1_MASK,    PPCVSX,	0,		{XT6, RA0, RB}},
XX1_MASK         6093 arch/powerpc/xmon/ppc-opc.c {"lxvx",	X(31,844),	XX1_MASK,    POWER8,	POWER9|PPCVSX3,	{XT6, RA0, RB}},
XX1_MASK         6120 arch/powerpc/xmon/ppc-opc.c {"lxvb16x",	X(31,876),	XX1_MASK,    PPCVSX3,	0,		{XT6, RA0, RB}},
XX1_MASK         6145 arch/powerpc/xmon/ppc-opc.c {"stxvw4x",	X(31,908),	XX1_MASK,    PPCVSX,	0,		{XS6, RA0, RB}},
XX1_MASK         6146 arch/powerpc/xmon/ppc-opc.c {"stxsibx",	X(31,909),	XX1_MASK,    PPCVSX3,	0,		{XS6, RA0, RB}},
XX1_MASK         6189 arch/powerpc/xmon/ppc-opc.c {"stxvh8x",	X(31,940),	XX1_MASK,    PPCVSX3,	0,		{XS6, RA0, RB}},
XX1_MASK         6190 arch/powerpc/xmon/ppc-opc.c {"stxsihx",	X(31,941),	XX1_MASK,    PPCVSX3,	0,		{XS6, RA0, RB}},
XX1_MASK         6222 arch/powerpc/xmon/ppc-opc.c {"stxvd2x",	X(31,972),	XX1_MASK,    PPCVSX,	0,		{XS6, RA0, RB}},
XX1_MASK         6223 arch/powerpc/xmon/ppc-opc.c {"stxvx",	X(31,972),	XX1_MASK,    POWER8,	POWER9|PPCVSX3,	{XS6, RA0, RB}},
XX1_MASK         6256 arch/powerpc/xmon/ppc-opc.c {"stxvb16x",	X(31,1004),	XX1_MASK,    PPCVSX3,	0,		{XS6, RA0, RB}},
XX1_MASK         6538 arch/powerpc/xmon/ppc-opc.c {"xxspltib",	X(60,360),   XX1_MASK|3<<19, PPCVSX3,	PPCVLE,		{XT6, IMM8}},
XX1_MASK         6636 arch/powerpc/xmon/ppc-opc.c {"xsiexpdp",	X(60,918),	XX1_MASK,    PPCVSX3,	PPCVLE,		{XT6, RA, RB}},