XTFPGA_CLKFRQ_VADDR   16 arch/xtensa/platforms/xtfpga/include/platform/serial.h #define BASE_BAUD (*(long *)XTFPGA_CLKFRQ_VADDR / 16)
XTFPGA_CLKFRQ_VADDR   79 arch/xtensa/platforms/xtfpga/setup.c 	ccount_freq = *(long *)XTFPGA_CLKFRQ_VADDR;
XTFPGA_CLKFRQ_VADDR  282 arch/xtensa/platforms/xtfpga/setup.c 	serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR;
XTFPGA_CLKFRQ_VADDR  292 arch/xtensa/platforms/xtfpga/setup.c 	ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR;