XTENSA_PMU_MASK 59 arch/xtensa/kernel/perf_event.c [PERF_COUNT_HW_CPU_CYCLES] = XTENSA_PMU_MASK(0, 0x1), XTENSA_PMU_MASK 60 arch/xtensa/kernel/perf_event.c [PERF_COUNT_HW_INSTRUCTIONS] = XTENSA_PMU_MASK(2, 0xffff), XTENSA_PMU_MASK 61 arch/xtensa/kernel/perf_event.c [PERF_COUNT_HW_CACHE_REFERENCES] = XTENSA_PMU_MASK(10, 0x1), XTENSA_PMU_MASK 62 arch/xtensa/kernel/perf_event.c [PERF_COUNT_HW_CACHE_MISSES] = XTENSA_PMU_MASK(12, 0x1), XTENSA_PMU_MASK 64 arch/xtensa/kernel/perf_event.c [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XTENSA_PMU_MASK(2, 0x490), XTENSA_PMU_MASK 66 arch/xtensa/kernel/perf_event.c [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XTENSA_PMU_MASK(4, 0x1ff), XTENSA_PMU_MASK 68 arch/xtensa/kernel/perf_event.c [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = XTENSA_PMU_MASK(3, 0x1ff), XTENSA_PMU_MASK 76 arch/xtensa/kernel/perf_event.c [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(10, 0x1), XTENSA_PMU_MASK 77 arch/xtensa/kernel/perf_event.c [C(RESULT_MISS)] = XTENSA_PMU_MASK(10, 0x2), XTENSA_PMU_MASK 80 arch/xtensa/kernel/perf_event.c [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(11, 0x1), XTENSA_PMU_MASK 81 arch/xtensa/kernel/perf_event.c [C(RESULT_MISS)] = XTENSA_PMU_MASK(11, 0x2), XTENSA_PMU_MASK 86 arch/xtensa/kernel/perf_event.c [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(8, 0x1), XTENSA_PMU_MASK 87 arch/xtensa/kernel/perf_event.c [C(RESULT_MISS)] = XTENSA_PMU_MASK(8, 0x2), XTENSA_PMU_MASK 92 arch/xtensa/kernel/perf_event.c [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(9, 0x1), XTENSA_PMU_MASK 93 arch/xtensa/kernel/perf_event.c [C(RESULT_MISS)] = XTENSA_PMU_MASK(9, 0x8), XTENSA_PMU_MASK 98 arch/xtensa/kernel/perf_event.c [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(7, 0x1), XTENSA_PMU_MASK 99 arch/xtensa/kernel/perf_event.c [C(RESULT_MISS)] = XTENSA_PMU_MASK(7, 0x8),