XIIC_REG_OFFSET 85 drivers/i2c/busses/i2c-xiic.c #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ XIIC_REG_OFFSET 86 drivers/i2c/busses/i2c-xiic.c #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ XIIC_REG_OFFSET 87 drivers/i2c/busses/i2c-xiic.c #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ XIIC_REG_OFFSET 88 drivers/i2c/busses/i2c-xiic.c #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ XIIC_REG_OFFSET 89 drivers/i2c/busses/i2c-xiic.c #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ XIIC_REG_OFFSET 90 drivers/i2c/busses/i2c-xiic.c #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ XIIC_REG_OFFSET 91 drivers/i2c/busses/i2c-xiic.c #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ XIIC_REG_OFFSET 92 drivers/i2c/busses/i2c-xiic.c #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ XIIC_REG_OFFSET 93 drivers/i2c/busses/i2c-xiic.c #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ XIIC_REG_OFFSET 94 drivers/i2c/busses/i2c-xiic.c #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */