XFM_SF 115 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ XFM_SF 116 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ XFM_SF 117 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ XFM_SF 118 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ XFM_SF 119 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ XFM_SF 120 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ XFM_SF 121 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ XFM_SF 122 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ XFM_SF 123 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ XFM_SF 124 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ XFM_SF 125 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ XFM_SF 126 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ XFM_SF 127 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ XFM_SF 128 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \ XFM_SF 129 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ XFM_SF 130 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ XFM_SF 131 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ XFM_SF 132 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ XFM_SF 133 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ XFM_SF 134 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ XFM_SF 135 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ XFM_SF 136 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ XFM_SF 137 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ XFM_SF 138 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ XFM_SF 139 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ XFM_SF 140 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ XFM_SF 141 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ XFM_SF 142 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ XFM_SF 143 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ XFM_SF 144 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ XFM_SF 145 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ XFM_SF 146 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ XFM_SF 147 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ XFM_SF 148 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ XFM_SF 149 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ XFM_SF 150 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ XFM_SF 151 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ XFM_SF 152 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ XFM_SF 153 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ XFM_SF 154 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ XFM_SF 155 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ XFM_SF 156 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ XFM_SF 157 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ XFM_SF 158 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ XFM_SF 159 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \ XFM_SF 160 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ XFM_SF 161 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ XFM_SF 162 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ XFM_SF 163 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ XFM_SF 164 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ XFM_SF 165 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ XFM_SF 166 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ XFM_SF 167 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ XFM_SF 168 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ XFM_SF 169 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ XFM_SF 170 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ XFM_SF 171 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ XFM_SF 172 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ XFM_SF 173 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ XFM_SF 174 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ XFM_SF 175 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ XFM_SF 176 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ XFM_SF 177 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ XFM_SF 178 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ XFM_SF 179 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ XFM_SF 180 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ XFM_SF 181 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ XFM_SF 182 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ XFM_SF 183 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ XFM_SF 184 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ XFM_SF 185 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ XFM_SF 186 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ XFM_SF 187 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ XFM_SF 188 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ XFM_SF 189 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ XFM_SF 190 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh) XFM_SF 200 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ XFM_SF 201 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ XFM_SF 202 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ XFM_SF 203 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ XFM_SF 204 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ XFM_SF 205 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh) XFM_SF 208 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ XFM_SF 209 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ XFM_SF 210 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ XFM_SF 211 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ XFM_SF 212 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ XFM_SF 213 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ XFM_SF 214 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ XFM_SF 215 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ XFM_SF 216 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ XFM_SF 217 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ XFM_SF 218 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ XFM_SF 219 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ XFM_SF 220 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ XFM_SF 221 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \ XFM_SF 222 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ XFM_SF 223 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ XFM_SF 224 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ XFM_SF 225 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ XFM_SF 226 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ XFM_SF 227 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ XFM_SF 228 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ XFM_SF 229 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ XFM_SF 230 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ XFM_SF 231 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ XFM_SF 232 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ XFM_SF 233 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ XFM_SF 234 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ XFM_SF 235 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ XFM_SF 236 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ XFM_SF 237 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ XFM_SF 238 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ XFM_SF 239 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ XFM_SF 240 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ XFM_SF 241 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ XFM_SF 242 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ XFM_SF 243 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ XFM_SF 244 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ XFM_SF 245 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ XFM_SF 246 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ XFM_SF 247 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ XFM_SF 248 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ XFM_SF 249 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ XFM_SF 250 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ XFM_SF 251 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ XFM_SF 252 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \ XFM_SF 253 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ XFM_SF 254 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ XFM_SF 255 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ XFM_SF 256 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ XFM_SF 257 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ XFM_SF 258 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ XFM_SF 259 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ XFM_SF 260 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ XFM_SF 261 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ XFM_SF 262 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ XFM_SF 263 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ XFM_SF 264 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ XFM_SF 265 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ XFM_SF 266 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ XFM_SF 267 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ XFM_SF 268 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ XFM_SF 269 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ XFM_SF 270 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ XFM_SF 271 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ XFM_SF 272 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ XFM_SF 273 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ XFM_SF 274 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ XFM_SF 275 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ XFM_SF 276 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ XFM_SF 277 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ XFM_SF 278 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ XFM_SF 279 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ XFM_SF 280 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ XFM_SF 281 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ XFM_SF 282 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ XFM_SF 283 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \ XFM_SF 284 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ XFM_SF 285 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ XFM_SF 286 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ XFM_SF 287 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ XFM_SF 288 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh)