XCHAL_ICACHE_SIZE   21 arch/xtensa/include/asm/cache.h #define ICACHE_WAY_SIZE	(XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
XCHAL_ICACHE_SIZE   95 arch/xtensa/include/asm/cacheasm.h #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
XCHAL_ICACHE_SIZE   96 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \
XCHAL_ICACHE_SIZE  135 arch/xtensa/include/asm/cacheasm.h #if XCHAL_ICACHE_SIZE
XCHAL_ICACHE_SIZE  136 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \
XCHAL_ICACHE_SIZE  173 arch/xtensa/include/asm/cacheasm.h #if XCHAL_ICACHE_SIZE
XCHAL_ICACHE_SIZE  210 arch/xtensa/include/asm/cacheasm.h #if XCHAL_ICACHE_SIZE
XCHAL_ICACHE_SIZE  699 arch/xtensa/kernel/setup.c 		     XCHAL_ICACHE_SIZE,