XCHAL_ICACHE_LINEWIDTH   23 arch/xtensa/include/asm/cache.h #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
XCHAL_ICACHE_LINEWIDTH   97 arch/xtensa/include/asm/cacheasm.h 		XCHAL_ICACHE_LINEWIDTH 240
XCHAL_ICACHE_LINEWIDTH  137 arch/xtensa/include/asm/cacheasm.h 			 XCHAL_ICACHE_LINEWIDTH 1020
XCHAL_ICACHE_LINEWIDTH  174 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
XCHAL_ICACHE_LINEWIDTH  211 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020