XCHAL_DCACHE_SIZE   20 arch/xtensa/include/asm/cache.h #define DCACHE_WAY_SIZE	(XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
XCHAL_DCACHE_SIZE   85 arch/xtensa/include/asm/cacheasm.h #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
XCHAL_DCACHE_SIZE   86 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \
XCHAL_DCACHE_SIZE  105 arch/xtensa/include/asm/cacheasm.h #if XCHAL_DCACHE_SIZE
XCHAL_DCACHE_SIZE  106 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \
XCHAL_DCACHE_SIZE  115 arch/xtensa/include/asm/cacheasm.h #if XCHAL_DCACHE_SIZE
XCHAL_DCACHE_SIZE  116 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \
XCHAL_DCACHE_SIZE  125 arch/xtensa/include/asm/cacheasm.h #if XCHAL_DCACHE_SIZE
XCHAL_DCACHE_SIZE  126 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \
XCHAL_DCACHE_SIZE  146 arch/xtensa/include/asm/cacheasm.h #if XCHAL_DCACHE_SIZE
XCHAL_DCACHE_SIZE  155 arch/xtensa/include/asm/cacheasm.h #if XCHAL_DCACHE_SIZE
XCHAL_DCACHE_SIZE  164 arch/xtensa/include/asm/cacheasm.h #if XCHAL_DCACHE_SIZE
XCHAL_DCACHE_SIZE  183 arch/xtensa/include/asm/cacheasm.h #if XCHAL_DCACHE_SIZE
XCHAL_DCACHE_SIZE  192 arch/xtensa/include/asm/cacheasm.h #if XCHAL_DCACHE_SIZE
XCHAL_DCACHE_SIZE  201 arch/xtensa/include/asm/cacheasm.h #if XCHAL_DCACHE_SIZE
XCHAL_DCACHE_SIZE  702 arch/xtensa/kernel/setup.c 		     XCHAL_DCACHE_SIZE);