XCHAL_DCACHE_LINEWIDTH   16 arch/xtensa/include/asm/cache.h #define L1_CACHE_SHIFT	XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH   22 arch/xtensa/include/asm/cache.h #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
XCHAL_DCACHE_LINEWIDTH   87 arch/xtensa/include/asm/cacheasm.h 		XCHAL_DCACHE_LINEWIDTH 240
XCHAL_DCACHE_LINEWIDTH  107 arch/xtensa/include/asm/cacheasm.h 		XCHAL_DCACHE_LINEWIDTH 240
XCHAL_DCACHE_LINEWIDTH  117 arch/xtensa/include/asm/cacheasm.h 		XCHAL_DCACHE_LINEWIDTH 240
XCHAL_DCACHE_LINEWIDTH  127 arch/xtensa/include/asm/cacheasm.h 			 XCHAL_DCACHE_LINEWIDTH 1020
XCHAL_DCACHE_LINEWIDTH  147 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  156 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  165 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
XCHAL_DCACHE_LINEWIDTH  184 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020
XCHAL_DCACHE_LINEWIDTH  193 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020
XCHAL_DCACHE_LINEWIDTH  202 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020