X86_PMC_IDX_MAX   267 arch/x86/events/amd/core.c static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
X86_PMC_IDX_MAX   268 arch/x86/events/amd/core.c static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
X86_PMC_IDX_MAX   675 arch/x86/events/amd/core.c 	active = __bitmap_weight(cpuc->active_mask, X86_PMC_IDX_MAX);
X86_PMC_IDX_MAX   701 arch/x86/events/core.c 	unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
X86_PMC_IDX_MAX   783 arch/x86/events/core.c 		for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
X86_PMC_IDX_MAX   874 arch/x86/events/core.c 	unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
X86_PMC_IDX_MAX   879 arch/x86/events/core.c 	bitmap_zero(used_mask, X86_PMC_IDX_MAX);
X86_PMC_IDX_MAX   895 arch/x86/events/core.c 	for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
X86_PMC_IDX_MAX  1185 arch/x86/events/core.c static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
X86_PMC_IDX_MAX  1271 arch/x86/events/core.c 	int assign[X86_PMC_IDX_MAX];
X86_PMC_IDX_MAX  1945 arch/x86/events/core.c 	int assign[X86_PMC_IDX_MAX];
X86_PMC_IDX_MAX  2401 arch/x86/events/intel/core.c 	for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
X86_PMC_IDX_MAX  2979 arch/x86/events/intel/core.c 	for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
X86_PMC_IDX_MAX  3031 arch/x86/events/intel/core.c 		bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
X86_PMC_IDX_MAX  3659 arch/x86/events/intel/core.c 		size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
X86_PMC_IDX_MAX   242 arch/x86/events/intel/knc.c 	for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
X86_PMC_IDX_MAX  1208 arch/x86/events/intel/p4.c 	unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
X86_PMC_IDX_MAX  1218 arch/x86/events/intel/p4.c 	bitmap_zero(used_mask, X86_PMC_IDX_MAX);
X86_PMC_IDX_MAX    49 arch/x86/events/perf_event.h 		unsigned long	idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
X86_PMC_IDX_MAX    85 arch/x86/events/perf_event.h 	struct perf_event *owners[X86_PMC_IDX_MAX];
X86_PMC_IDX_MAX    86 arch/x86/events/perf_event.h 	struct event_constraint event_constraints[X86_PMC_IDX_MAX];
X86_PMC_IDX_MAX   160 arch/x86/events/perf_event.h 	enum intel_excl_state_type state[X86_PMC_IDX_MAX];
X86_PMC_IDX_MAX   191 arch/x86/events/perf_event.h 	struct perf_event	*events[X86_PMC_IDX_MAX]; /* in counter order */
X86_PMC_IDX_MAX   192 arch/x86/events/perf_event.h 	unsigned long		active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
X86_PMC_IDX_MAX   193 arch/x86/events/perf_event.h 	unsigned long		running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
X86_PMC_IDX_MAX   201 arch/x86/events/perf_event.h 	int			assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
X86_PMC_IDX_MAX   202 arch/x86/events/perf_event.h 	u64			tags[X86_PMC_IDX_MAX];
X86_PMC_IDX_MAX   204 arch/x86/events/perf_event.h 	struct perf_event	*event_list[X86_PMC_IDX_MAX]; /* in enabled order */
X86_PMC_IDX_MAX   205 arch/x86/events/perf_event.h 	struct event_constraint	*event_constraint[X86_PMC_IDX_MAX];
X86_PMC_IDX_MAX   246 arch/x86/events/perf_event.h 	struct perf_guest_switch_msr	guest_switch_msrs[X86_PMC_IDX_MAX];
X86_PMC_IDX_MAX   261 arch/x86/kvm/pmu.c 	for_each_set_bit(bit, (unsigned long *)&bitmask, X86_PMC_IDX_MAX) {
X86_PMC_IDX_MAX    63 arch/x86/kvm/vmx/pmu_intel.c 	for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)