WZRD_CLK_CFG_REG  187 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c 	reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
WZRD_CLK_CFG_REG  189 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c 	reg |= readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2)) &
WZRD_CLK_CFG_REG  195 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c 	reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
WZRD_CLK_CFG_REG  214 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c 	reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
WZRD_CLK_CFG_REG  243 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c 		reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2) + i * 12);