WREG32_SOC15_OFFSET 1625 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
WREG32_SOC15_OFFSET 1626 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
WREG32_SOC15_OFFSET 1627 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
WREG32_SOC15_OFFSET 1628 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
WREG32_SOC15_OFFSET 1643 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
WREG32_SOC15_OFFSET 1644 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
WREG32_SOC15_OFFSET 1645 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
WREG32_SOC15_OFFSET 1646 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
WREG32_SOC15_OFFSET 2474 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
WREG32_SOC15_OFFSET 2475 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
WREG32_SOC15_OFFSET 2476 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
WREG32_SOC15_OFFSET 2477 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
WREG32_SOC15_OFFSET 2492 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
WREG32_SOC15_OFFSET 2493 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
WREG32_SOC15_OFFSET 2494 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
WREG32_SOC15_OFFSET 2495 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
WREG32_SOC15_OFFSET   45 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
WREG32_SOC15_OFFSET   48 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
WREG32_SOC15_OFFSET  241 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
WREG32_SOC15_OFFSET  242 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
WREG32_SOC15_OFFSET  243 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
WREG32_SOC15_OFFSET  244 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,
WREG32_SOC15_OFFSET  246 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
WREG32_SOC15_OFFSET  256 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
WREG32_SOC15_OFFSET  258 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
WREG32_SOC15_OFFSET  298 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);
WREG32_SOC15_OFFSET  229 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp);
WREG32_SOC15_OFFSET  230 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
WREG32_SOC15_OFFSET  231 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
WREG32_SOC15_OFFSET  232 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,
WREG32_SOC15_OFFSET  234 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
WREG32_SOC15_OFFSET  244 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
WREG32_SOC15_OFFSET  246 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
WREG32_SOC15_OFFSET  286 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0);
WREG32_SOC15_OFFSET   65 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
WREG32_SOC15_OFFSET   68 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
WREG32_SOC15_OFFSET  273 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
WREG32_SOC15_OFFSET  274 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
WREG32_SOC15_OFFSET  275 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
WREG32_SOC15_OFFSET  276 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
WREG32_SOC15_OFFSET  278 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
WREG32_SOC15_OFFSET  288 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
WREG32_SOC15_OFFSET  290 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
WREG32_SOC15_OFFSET  343 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
WREG32_SOC15_OFFSET  219 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp);
WREG32_SOC15_OFFSET  220 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
WREG32_SOC15_OFFSET  221 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
WREG32_SOC15_OFFSET  222 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
WREG32_SOC15_OFFSET  224 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
WREG32_SOC15_OFFSET  234 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
WREG32_SOC15_OFFSET  236 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
WREG32_SOC15_OFFSET  276 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0);
WREG32_SOC15_OFFSET   65 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET   70 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET   84 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET   88 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET   93 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET   97 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  110 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE,
WREG32_SOC15_OFFSET  113 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP,
WREG32_SOC15_OFFSET  116 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT,
WREG32_SOC15_OFFSET  121 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  125 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  133 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  137 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  143 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  147 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  157 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
WREG32_SOC15_OFFSET  185 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
WREG32_SOC15_OFFSET  209 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
WREG32_SOC15_OFFSET  218 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
WREG32_SOC15_OFFSET  231 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
WREG32_SOC15_OFFSET  239 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4,
WREG32_SOC15_OFFSET  252 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
WREG32_SOC15_OFFSET  259 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  262 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  266 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  269 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  273 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  276 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 	WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  315 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
WREG32_SOC15_OFFSET  318 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  321 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  324 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  328 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  341 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  345 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  363 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  367 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  396 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  410 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  419 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
WREG32_SOC15_OFFSET  421 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
WREG32_SOC15_OFFSET  484 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 		WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  550 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
WREG32_SOC15_OFFSET  578 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 				WREG32_SOC15_OFFSET(MMHUB, 0,
WREG32_SOC15_OFFSET  606 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,