WREG32_SOC15_DPG_MODE 368 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, WREG32_SOC15_DPG_MODE 371 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, WREG32_SOC15_DPG_MODE 374 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, WREG32_SOC15_DPG_MODE 378 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, WREG32_SOC15_DPG_MODE 380 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, WREG32_SOC15_DPG_MODE 383 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, WREG32_SOC15_DPG_MODE 387 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); WREG32_SOC15_DPG_MODE 390 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, WREG32_SOC15_DPG_MODE 392 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, WREG32_SOC15_DPG_MODE 394 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, WREG32_SOC15_DPG_MODE 396 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, WREG32_SOC15_DPG_MODE 400 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, WREG32_SOC15_DPG_MODE 403 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, WREG32_SOC15_DPG_MODE 406 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); WREG32_SOC15_DPG_MODE 407 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, WREG32_SOC15_DPG_MODE 411 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, WREG32_SOC15_DPG_MODE 413 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, WREG32_SOC15_DPG_MODE 415 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, WREG32_SOC15_DPG_MODE 417 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, WREG32_SOC15_DPG_MODE 419 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, WREG32_SOC15_DPG_MODE 421 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, WREG32_SOC15_DPG_MODE 423 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, WREG32_SOC15_DPG_MODE 425 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, WREG32_SOC15_DPG_MODE 427 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, WREG32_SOC15_DPG_MODE 429 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, WREG32_SOC15_DPG_MODE 644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); WREG32_SOC15_DPG_MODE 646 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); WREG32_SOC15_DPG_MODE 675 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); WREG32_SOC15_DPG_MODE 678 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); WREG32_SOC15_DPG_MODE 681 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); WREG32_SOC15_DPG_MODE 684 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); WREG32_SOC15_DPG_MODE 995 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); WREG32_SOC15_DPG_MODE 998 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, WREG32_SOC15_DPG_MODE 1002 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, WREG32_SOC15_DPG_MODE 1016 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); WREG32_SOC15_DPG_MODE 1018 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL, WREG32_SOC15_DPG_MODE 1021 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, WREG32_SOC15_DPG_MODE 1027 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, WREG32_SOC15_DPG_MODE 1033 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, WREG32_SOC15_DPG_MODE 1040 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); WREG32_SOC15_DPG_MODE 1041 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); WREG32_SOC15_DPG_MODE 1044 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); WREG32_SOC15_DPG_MODE 1047 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, WREG32_SOC15_DPG_MODE 1052 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, WREG32_SOC15_DPG_MODE 1057 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, WREG32_SOC15_DPG_MODE 1069 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); WREG32_SOC15_DPG_MODE 1070 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); WREG32_SOC15_DPG_MODE 1073 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN,