WREG32_SMC_P 7458 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); WREG32_SMC_P 7463 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); WREG32_SMC_P 7474 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); WREG32_SMC_P 7490 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, WREG32_SMC_P 7495 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK, WREG32_SMC_P 7500 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, WREG32_SMC_P 7512 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); WREG32_SMC_P 7515 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK, WREG32_SMC_P 7519 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, WREG32_SMC_P 7521 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK); WREG32_SMC_P 7524 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); WREG32_SMC_P 7533 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK); WREG32_SMC_P 7536 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); WREG32_SMC_P 7539 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK); WREG32_SMC_P 7542 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK); WREG32_SMC_P 7545 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, WREG32_SMC_P 7553 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); WREG32_SMC_P 7558 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK); WREG32_SMC_P 7565 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,