WREG32_SMC 96 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c return WREG32_SMC(index, value); WREG32_SMC 444 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c WREG32_SMC(*pos, value); WREG32_SMC 921 drivers/gpu/drm/amd/amdgpu/cik.c WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); WREG32_SMC 932 drivers/gpu/drm/amd/amdgpu/cik.c WREG32_SMC(ixROM_CNTL, rom_cntl); WREG32_SMC 1322 drivers/gpu/drm/amd/amdgpu/cik.c WREG32_SMC(cntl_reg, tmp); WREG32_SMC 1371 drivers/gpu/drm/amd/amdgpu/cik.c WREG32_SMC(ixCG_ECLK_CNTL, tmp); WREG32_SMC 1657 drivers/gpu/drm/amd/amdgpu/cik.c WREG32_SMC(ixTHM_CLK_CNTL, data); WREG32_SMC 1665 drivers/gpu/drm/amd/amdgpu/cik.c WREG32_SMC(ixMISC_CLK_CTRL, data); WREG32_SMC 1670 drivers/gpu/drm/amd/amdgpu/cik.c WREG32_SMC(ixCG_CLKPIN_CNTL, data); WREG32_SMC 1675 drivers/gpu/drm/amd/amdgpu/cik.c WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); WREG32_SMC 1681 drivers/gpu/drm/amd/amdgpu/cik.c WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); WREG32_SMC 793 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); WREG32_SMC 403 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(local_cac_reg->cntl, data); WREG32_SMC 443 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(config_regs->offset, data); WREG32_SMC 534 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0); WREG32_SMC 535 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0); WREG32_SMC 538 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0); WREG32_SMC 539 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0); WREG32_SMC 542 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0); WREG32_SMC 543 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0); WREG32_SMC 546 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0); WREG32_SMC 547 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0); WREG32_SMC 550 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0); WREG32_SMC 551 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0); WREG32_SMC 554 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0); WREG32_SMC 555 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0); WREG32_SMC 653 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100); WREG32_SMC 658 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0); WREG32_SMC 730 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixGENERAL_PWRMGT, tmp); WREG32_SMC 748 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); WREG32_SMC 758 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); WREG32_SMC 2516 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1); WREG32_SMC 2541 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp); WREG32_SMC 3151 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); WREG32_SMC 3156 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); WREG32_SMC 3168 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); WREG32_SMC 3173 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); WREG32_SMC 2865 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_SMC(offset, data); WREG32_SMC 7517 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); WREG32_SMC 7522 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); WREG32_SMC 7534 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); WREG32_SMC 7539 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); WREG32_SMC 117 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); WREG32_SMC 131 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); WREG32_SMC 150 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); WREG32_SMC 1689 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); WREG32_SMC 883 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); WREG32_SMC 405 drivers/gpu/drm/amd/amdgpu/vi.c WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); WREG32_SMC 416 drivers/gpu/drm/amd/amdgpu/vi.c WREG32_SMC(ixROM_CNTL, rom_cntl); WREG32_SMC 746 drivers/gpu/drm/amd/amdgpu/vi.c WREG32_SMC(cntl_reg, tmp); WREG32_SMC 836 drivers/gpu/drm/amd/amdgpu/vi.c WREG32_SMC(reg_ctrl, tmp); WREG32_SMC 1441 drivers/gpu/drm/amd/amdgpu/vi.c WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); WREG32_SMC 600 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(config_regs->offset, data); WREG32_SMC 890 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_THERMAL_INT, tmp); WREG32_SMC 897 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_THERMAL_CTRL, tmp); WREG32_SMC 914 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_THERMAL_INT, thermal_int); WREG32_SMC 923 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_THERMAL_INT, thermal_int); WREG32_SMC 950 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL2, tmp); WREG32_SMC 954 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL2, tmp); WREG32_SMC 1128 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL0, tmp); WREG32_SMC 1205 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_TACH_CTRL, tmp); WREG32_SMC 1221 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL2, tmp); WREG32_SMC 1225 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL2, tmp); WREG32_SMC 1245 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_TACH_CTRL, tmp); WREG32_SMC 1250 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FDO_CTRL2, tmp); WREG32_SMC 1413 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_THERMAL_CTRL, tmp); WREG32_SMC 1421 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(GENERAL_PWRMGT, tmp); WREG32_SMC 1425 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(GENERAL_PWRMGT, tmp); WREG32_SMC 1499 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(LCAC_MC0_CNTL, 0x05); WREG32_SMC 1500 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(LCAC_MC1_CNTL, 0x05); WREG32_SMC 1501 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(LCAC_CPL_CNTL, 0x100005); WREG32_SMC 1505 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(LCAC_MC0_CNTL, 0x400005); WREG32_SMC 1506 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(LCAC_MC1_CNTL, 0x400005); WREG32_SMC 1507 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(LCAC_CPL_CNTL, 0x500005); WREG32_SMC 1535 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(GENERAL_PWRMGT, tmp); WREG32_SMC 1539 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); WREG32_SMC 1596 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(GENERAL_PWRMGT, tmp); WREG32_SMC 1600 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); WREG32_SMC 1627 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); WREG32_SMC 1913 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(GENERAL_PWRMGT, tmp); WREG32_SMC 1922 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(GENERAL_PWRMGT, tmp); WREG32_SMC 1999 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); WREG32_SMC 2010 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp); WREG32_SMC 2028 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(GENERAL_PWRMGT, tmp); WREG32_SMC 2033 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp); WREG32_SMC 2037 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(GENERAL_PWRMGT, tmp); WREG32_SMC 2043 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); WREG32_SMC 2054 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); WREG32_SMC 2063 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); WREG32_SMC 2065 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0); WREG32_SMC 2066 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1); WREG32_SMC 2067 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2); WREG32_SMC 2068 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3); WREG32_SMC 2069 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4); WREG32_SMC 2070 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5); WREG32_SMC 2071 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6); WREG32_SMC 2072 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7); WREG32_SMC 2081 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); WREG32_SMC 2083 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_0, 0); WREG32_SMC 2084 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_1, 0); WREG32_SMC 2085 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_2, 0); WREG32_SMC 2086 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_3, 0); WREG32_SMC 2087 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_4, 0); WREG32_SMC 2088 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_5, 0); WREG32_SMC 2089 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_6, 0); WREG32_SMC 2090 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_FTV_7, 0); WREG32_SMC 2102 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1); WREG32_SMC 3585 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); WREG32_SMC 4093 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(DPM_TABLE_475, tmp); WREG32_SMC 4131 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(DPM_TABLE_475, tmp); WREG32_SMC 4161 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(DPM_TABLE_475, tmp); WREG32_SMC 4794 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(GENERAL_PWRMGT, tmp); WREG32_SMC 5873 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CNB_PWRMGT_CNTL, tmp); WREG32_SMC 119 drivers/gpu/drm/radeon/ci_smc.c WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); WREG32_SMC 127 drivers/gpu/drm/radeon/ci_smc.c WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); WREG32_SMC 143 drivers/gpu/drm/radeon/ci_smc.c WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); WREG32_SMC 152 drivers/gpu/drm/radeon/ci_smc.c WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); WREG32_SMC 9443 drivers/gpu/drm/radeon/cik.c WREG32_SMC(cntl_reg, tmp); WREG32_SMC 9490 drivers/gpu/drm/radeon/cik.c WREG32_SMC(CG_ECLK_CNTL, tmp); WREG32_SMC 9765 drivers/gpu/drm/radeon/cik.c WREG32_SMC(THM_CLK_CNTL, data); WREG32_SMC 9771 drivers/gpu/drm/radeon/cik.c WREG32_SMC(MISC_CLK_CTRL, data); WREG32_SMC 9776 drivers/gpu/drm/radeon/cik.c WREG32_SMC(CG_CLKPIN_CNTL, data); WREG32_SMC 9781 drivers/gpu/drm/radeon/cik.c WREG32_SMC(CG_CLKPIN_CNTL_2, data); WREG32_SMC 9787 drivers/gpu/drm/radeon/cik.c WREG32_SMC(MPLL_BYPASSCLK_SEL, data); WREG32_SMC 277 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(local_cac_reg->cntl, data); WREG32_SMC 317 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(config_regs->offset, data); WREG32_SMC 408 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_SX0_OVR_SEL, 0); WREG32_SMC 409 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_SX0_OVR_VAL, 0); WREG32_SMC 412 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_MC0_OVR_SEL, 0); WREG32_SMC 413 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_MC0_OVR_VAL, 0); WREG32_SMC 416 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_MC1_OVR_SEL, 0); WREG32_SMC 417 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_MC1_OVR_VAL, 0); WREG32_SMC 420 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_MC2_OVR_SEL, 0); WREG32_SMC 421 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_MC2_OVR_VAL, 0); WREG32_SMC 424 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_MC3_OVR_SEL, 0); WREG32_SMC 425 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_MC3_OVR_VAL, 0); WREG32_SMC 428 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_CPL_OVR_SEL, 0); WREG32_SMC 429 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(LCAC_CPL_OVR_VAL, 0); WREG32_SMC 527 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(CG_FTV_0, 0x3FFFC100); WREG32_SMC 532 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(CG_FTV_0, 0); WREG32_SMC 650 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(GENERAL_PWRMGT, tmp); WREG32_SMC 667 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); WREG32_SMC 676 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); WREG32_SMC 1183 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); WREG32_SMC 2449 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1); WREG32_SMC 2473 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(CG_THERMAL_INT_CTRL, tmp); WREG32_SMC 2563 drivers/gpu/drm/radeon/radeon.h WREG32_SMC(reg, tmp_); \ WREG32_SMC 5466 drivers/gpu/drm/radeon/si.c WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); WREG32_SMC 5467 drivers/gpu/drm/radeon/si.c WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); WREG32_SMC 5478 drivers/gpu/drm/radeon/si.c WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); WREG32_SMC 5479 drivers/gpu/drm/radeon/si.c WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); WREG32_SMC 2766 drivers/gpu/drm/radeon/si_dpm.c WREG32_SMC(offset, data); WREG32_SMC 119 drivers/gpu/drm/radeon/si_smc.c WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); WREG32_SMC 133 drivers/gpu/drm/radeon/si_smc.c WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); WREG32_SMC 149 drivers/gpu/drm/radeon/si_smc.c WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); WREG32_SMC 158 drivers/gpu/drm/radeon/si_smc.c WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); WREG32_SMC 384 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(GFX_POWER_GATING_CNTL, value); WREG32_SMC 508 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); WREG32_SMC 526 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(PM_I_CNTL_1, value); WREG32_SMC 531 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_S_PG_CNTL, value); WREG32_SMC 535 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_S_PG_CNTL, value); WREG32_SMC 539 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(PM_I_CNTL_1, value); WREG32_SMC 600 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); WREG32_SMC 610 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value); WREG32_SMC 622 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); WREG32_SMC 634 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); WREG32_SMC 647 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); WREG32_SMC 652 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); WREG32_SMC 664 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value); WREG32_SMC 676 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value); WREG32_SMC 688 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); WREG32_SMC 700 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); WREG32_SMC 712 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value); WREG32_SMC 744 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); WREG32_SMC 761 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_CNTL, value); WREG32_SMC 798 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_CNTL, sclk_dpm_cntl); WREG32_SMC 879 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_UVD_DPM_STATES, uvdstates); WREG32_SMC 894 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_UVD_DPM_CNTL, val); WREG32_SMC 1014 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_TTT, value); WREG32_SMC 1023 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(SMU_SCLK_DPM_TT_CNTL, value); WREG32_SMC 1041 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(PM_I_CNTL_1, value); WREG32_SMC 1198 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(NB_PSTATE_CONFIG, nbpsconfig); WREG32_SMC 1648 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_SMC(DC_CAC_VALUE, dc_cac_value); WREG32_SMC 66 drivers/gpu/drm/radeon/trinity_smc.c WREG32_SMC(SMU_SCRATCH0, 1); WREG32_SMC 68 drivers/gpu/drm/radeon/trinity_smc.c WREG32_SMC(SMU_SCRATCH0, 0); WREG32_SMC 75 drivers/gpu/drm/radeon/trinity_smc.c WREG32_SMC(SMU_SCRATCH0, n); WREG32_SMC 82 drivers/gpu/drm/radeon/trinity_smc.c WREG32_SMC(SMU_SCRATCH0, n);