WREG32_RLC        141 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
WREG32_RLC        142 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
WREG32_RLC        285 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);
WREG32_RLC        294 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
WREG32_RLC        300 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
WREG32_RLC        329 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
WREG32_RLC        331 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
WREG32_RLC        333 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
WREG32_RLC        335 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
WREG32_RLC        342 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
WREG32_RLC        347 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
WREG32_RLC        563 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
WREG32_RLC       2600 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
WREG32_RLC       2602 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
WREG32_RLC       2604 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
WREG32_RLC        460 drivers/gpu/drm/amd/amdgpu/soc15.c 			WREG32_RLC(reg, tmp);
WREG32_RLC        119 drivers/gpu/drm/amd/amdgpu/soc15_common.h 			WREG32_RLC(target_reg, value); \
WREG32_RLC        123 drivers/gpu/drm/amd/amdgpu/soc15_common.h     WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
WREG32_RLC        128 drivers/gpu/drm/amd/amdgpu/soc15_common.h     WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value)