WREG32_RCU        185 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
WREG32_RCU        186 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
WREG32_RCU        188 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
WREG32_RCU        189 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
WREG32_RCU        200 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
WREG32_RCU        205 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
WREG32_RCU        210 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
WREG32_RCU        215 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
WREG32_RCU        218 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
WREG32_RCU        230 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
WREG32_RCU        236 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
WREG32_RCU        241 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
WREG32_RCU        257 drivers/gpu/drm/radeon/sumo_dpm.c 	WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
WREG32_RCU        263 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
WREG32_RCU        268 drivers/gpu/drm/radeon/sumo_dpm.c 		WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
WREG32_RCU         80 drivers/gpu/drm/radeon/sumo_smc.c 		WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
WREG32_RCU         84 drivers/gpu/drm/radeon/sumo_smc.c 		WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
WREG32_RCU         88 drivers/gpu/drm/radeon/sumo_smc.c 		WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
WREG32_RCU        122 drivers/gpu/drm/radeon/sumo_smc.c 	WREG32_RCU(RCU_ALTVDDNB_NOTIFY, param);
WREG32_RCU        156 drivers/gpu/drm/radeon/sumo_smc.c 	WREG32_RCU(RCU_GNB_PWR_REP_TIMER_CNTL, timer_value);
WREG32_RCU        157 drivers/gpu/drm/radeon/sumo_smc.c 	WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin);
WREG32_RCU        158 drivers/gpu/drm/radeon/sumo_smc.c 	WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin);
WREG32_RCU        159 drivers/gpu/drm/radeon/sumo_smc.c 	WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit);
WREG32_RCU        160 drivers/gpu/drm/radeon/sumo_smc.c 	WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg);
WREG32_RCU        204 drivers/gpu/drm/radeon/sumo_smc.c 	WREG32_RCU(regoffset, sclk_dpm_tdp_limit);
WREG32_RCU        213 drivers/gpu/drm/radeon/sumo_smc.c 	WREG32_RCU(RCU_GPU_BOOST_DISABLE, boost_disable);