WREG32_P 1096 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) WREG32_P 1097 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) WREG32_P 1962 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, WREG32_P 1644 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset, WREG32_P 1936 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, WREG32_P 148 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); WREG32_P 1101 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); WREG32_P 1253 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); WREG32_P 1432 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); WREG32_P 368 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); WREG32_P 86 drivers/gpu/drm/amd/amdgpu/kv_smc.c WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, WREG32_P 3118 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); WREG32_P 3123 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); WREG32_P 3128 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); WREG32_P 3133 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); WREG32_P 3141 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); WREG32_P 3765 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); WREG32_P 3767 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); WREG32_P 3769 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); WREG32_P 3794 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); WREG32_P 3799 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); WREG32_P 3805 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); WREG32_P 3807 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); WREG32_P 4053 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); WREG32_P 4055 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); WREG32_P 4060 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); WREG32_P 4141 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); WREG32_P 4142 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, WREG32_P 4198 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); WREG32_P 4200 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); WREG32_P 4201 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); WREG32_P 4231 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); WREG32_P 4243 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); WREG32_P 4245 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); WREG32_P 4248 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); WREG32_P 4251 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); WREG32_P 6166 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); WREG32_P 6168 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); WREG32_P 6433 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); WREG32_P 6434 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); WREG32_P 6435 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); WREG32_P 42 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); WREG32_P 229 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); WREG32_P 239 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); WREG32_P 265 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); WREG32_P 271 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); WREG32_P 278 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); WREG32_P 306 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); WREG32_P 308 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); WREG32_P 310 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); WREG32_P 312 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); WREG32_P 329 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, WREG32_P 332 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); WREG32_P 343 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); WREG32_P 345 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); WREG32_P 369 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); WREG32_P 411 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); WREG32_P 424 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(0x3D49, 0, ~(1 << 2)); WREG32_P 426 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); WREG32_P 654 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, WREG32_P 301 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); WREG32_P 310 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); WREG32_P 313 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); WREG32_P 325 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); WREG32_P 355 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); WREG32_P 374 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, WREG32_P 377 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); WREG32_P 387 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); WREG32_P 390 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); WREG32_P 421 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); WREG32_P 439 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); WREG32_P 450 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); WREG32_P 577 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, WREG32_P 708 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); WREG32_P 803 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32_P(mmUVD_MASTINT_EN, WREG32_P 808 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); WREG32_P 872 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); WREG32_P 883 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); WREG32_P 942 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, WREG32_P 957 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, WREG32_P 961 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, WREG32_P 965 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), WREG32_P 1016 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, WREG32_P 1037 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), WREG32_P 1041 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, WREG32_P 1052 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), WREG32_P 1057 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, WREG32_P 1090 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, WREG32_P 1128 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), WREG32_P 1142 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, WREG32_P 130 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_SOFT_RESET, WREG32_P 134 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_SOFT_RESET, 0, WREG32_P 172 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); WREG32_P 173 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); WREG32_P 174 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); WREG32_P 178 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); WREG32_P 200 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); WREG32_P 236 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_STATUS, 1, ~1); WREG32_P 265 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_STATUS, 0, ~1); WREG32_P 291 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8)); WREG32_P 300 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001); WREG32_P 303 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_SOFT_RESET, 1, ~0x1); WREG32_P 527 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); WREG32_P 306 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001); WREG32_P 343 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001); WREG32_P 528 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); WREG32_P 529 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); WREG32_P 530 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); WREG32_P 534 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); WREG32_P 571 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); WREG32_P 711 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); WREG32_P 139 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), WREG32_P 143 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, WREG32_P 365 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK, WREG32_P 368 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001); WREG32_P 370 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, WREG32_P 377 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK); WREG32_P 391 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001); WREG32_P 394 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), WREG32_P 607 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16)); WREG32_P 608 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000); WREG32_P 609 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F); WREG32_P 613 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1); WREG32_P 653 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), 0x0, ~0x100); WREG32_P 654 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), WREG32_P 1020 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val, WREG32_P 801 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, WREG32_P 850 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, WREG32_P 854 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, WREG32_P 876 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), WREG32_P 880 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, WREG32_P 891 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), WREG32_P 895 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), WREG32_P 934 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, WREG32_P 1107 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, WREG32_P 1152 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), WREG32_P 1161 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, WREG32_P 1165 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), WREG32_P 1169 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), WREG32_P 1208 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, WREG32_P 705 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0, WREG32_P 709 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN), WREG32_P 741 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), WREG32_P 1081 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), WREG32_P 1085 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, WREG32_P 1125 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, WREG32_P 1129 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, WREG32_P 1159 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), WREG32_P 1163 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, WREG32_P 1175 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), WREG32_P 1180 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, WREG32_P 1253 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, WREG32_P 1300 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, WREG32_P 1304 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), WREG32_P 1309 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), WREG32_P 1314 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), WREG32_P 620 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0, WREG32_P 651 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), 0, WREG32_P 655 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(VCN, i, mmJPEG_SYS_INT_EN), WREG32_P 691 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), WREG32_P 703 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), WREG32_P 721 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0, WREG32_P 736 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), WREG32_P 740 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0, WREG32_P 791 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, WREG32_P 795 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), 0, WREG32_P 798 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, WREG32_P 818 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), WREG32_P 822 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, WREG32_P 835 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), WREG32_P 840 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0, WREG32_P 923 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), WREG32_P 928 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), WREG32_P 933 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0, WREG32_P 942 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), WREG32_P 1412 drivers/gpu/drm/radeon/atombios_crtc.c WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, WREG32_P 1629 drivers/gpu/drm/radeon/atombios_crtc.c WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, WREG32_P 1382 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); WREG32_P 1384 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); WREG32_P 1670 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(SCLK_PSKIP_CNTL, PSKIP_ON_ALLOW_STOP_HI(32), WREG32_P 1777 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK); WREG32_P 1781 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK); WREG32_P 1822 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK); WREG32_P 1825 drivers/gpu/drm/radeon/btc_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK); WREG32_P 1497 drivers/gpu/drm/radeon/ci_dpm.c WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN); WREG32_P 1543 drivers/gpu/drm/radeon/ci_dpm.c WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN); WREG32_P 42 drivers/gpu/drm/radeon/ci_smc.c WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); WREG32_P 230 drivers/gpu/drm/radeon/ci_smc.c WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); WREG32_P 240 drivers/gpu/drm/radeon/ci_smc.c WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); WREG32_P 7915 drivers/gpu/drm/radeon/cik.c WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); WREG32_P 93 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); WREG32_P 95 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); WREG32_P 104 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P 105 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); WREG32_P 106 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); WREG32_P 111 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower), WREG32_P 142 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN); WREG32_P 144 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); WREG32_P 146 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P 147 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); WREG32_P 148 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); WREG32_P 152 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN); WREG32_P 199 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); WREG32_P 200 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); WREG32_P 201 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); WREG32_P 202 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); WREG32_P 203 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); WREG32_P 204 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); WREG32_P 205 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE); WREG32_P 206 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE); WREG32_P 228 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); WREG32_P 231 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); WREG32_P 233 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); WREG32_P 234 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); WREG32_P 235 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); WREG32_P 236 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN); WREG32_P 242 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); WREG32_P 249 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); WREG32_P 251 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); WREG32_P 258 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); WREG32_P 260 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); WREG32_P 1103 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK); WREG32_P 1104 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK); WREG32_P 1106 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK); WREG32_P 1107 drivers/gpu/drm/radeon/cypress_dpm.c WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK); WREG32_P 180 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32_P(HDMI0_ACR_32_0 + offset, WREG32_P 183 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32_P(HDMI0_ACR_32_1 + offset, WREG32_P 187 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32_P(HDMI0_ACR_44_0 + offset, WREG32_P 190 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32_P(HDMI0_ACR_44_1 + offset, WREG32_P 194 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32_P(HDMI0_ACR_48_0 + offset, WREG32_P 197 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32_P(HDMI0_ACR_48_1 + offset, WREG32_P 1156 drivers/gpu/drm/radeon/evergreen.c WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK)); WREG32_P 1199 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 1204 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); WREG32_P 1208 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); WREG32_P 1219 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); WREG32_P 1222 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); WREG32_P 1223 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); WREG32_P 1226 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); WREG32_P 1235 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); WREG32_P 1238 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); WREG32_P 1241 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); WREG32_P 1244 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); WREG32_P 1247 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9); WREG32_P 1249 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9); WREG32_P 1252 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 1260 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); WREG32_P 1265 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); WREG32_P 1272 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 4847 drivers/gpu/drm/radeon/evergreen.c WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); WREG32_P 222 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, WREG32_P 83 drivers/gpu/drm/radeon/kv_smc.c WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); WREG32_P 1716 drivers/gpu/drm/radeon/ni.c WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); WREG32_P 1723 drivers/gpu/drm/radeon/ni.c WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); WREG32_P 2740 drivers/gpu/drm/radeon/ni.c WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK)); WREG32_P 1023 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); WREG32_P 1207 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P 1208 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); WREG32_P 1209 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); WREG32_P 1213 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower), WREG32_P 1543 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); WREG32_P 1548 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); WREG32_P 1553 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); WREG32_P 1558 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); WREG32_P 1566 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); WREG32_P 3503 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); WREG32_P 3505 drivers/gpu/drm/radeon/ni_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); WREG32_P 2746 drivers/gpu/drm/radeon/r100.c WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, WREG32_P 209 drivers/gpu/drm/radeon/r600.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 214 drivers/gpu/drm/radeon/r600.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( WREG32_P 218 drivers/gpu/drm/radeon/r600.c WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, WREG32_P 223 drivers/gpu/drm/radeon/r600.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); WREG32_P 248 drivers/gpu/drm/radeon/r600.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); WREG32_P 252 drivers/gpu/drm/radeon/r600.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, WREG32_P 256 drivers/gpu/drm/radeon/r600.c WREG32_P(CG_UPLL_FUNC_CNTL, WREG32_P 260 drivers/gpu/drm/radeon/r600.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 272 drivers/gpu/drm/radeon/r600.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); WREG32_P 277 drivers/gpu/drm/radeon/r600.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); WREG32_P 280 drivers/gpu/drm/radeon/r600.c WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); WREG32_P 287 drivers/gpu/drm/radeon/r600.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 247 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); WREG32_P 249 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P 269 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); WREG32_P 271 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); WREG32_P 277 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); WREG32_P 279 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); WREG32_P 284 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); WREG32_P 290 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); WREG32_P 292 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); WREG32_P 306 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); WREG32_P 308 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); WREG32_P 314 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); WREG32_P 316 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); WREG32_P 322 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN); WREG32_P 324 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN); WREG32_P 361 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); WREG32_P 363 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); WREG32_P 365 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); WREG32_P 367 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); WREG32_P 377 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_TPC, TPU(u), ~TPU_MASK); WREG32_P 382 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK); WREG32_P 387 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_SSP, CG_SSTU(u), ~CG_SSTU_MASK); WREG32_P 392 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK); WREG32_P 397 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_GIT, CG_GICST(t), ~CG_GICST_MASK); WREG32_P 402 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK); WREG32_P 407 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK); WREG32_P 412 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_CTX_CGTT3D_R, PHC(p), ~PHC_MASK); WREG32_P 417 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_CTX_CGTT3D_R, SDC(s), ~SDC_MASK); WREG32_P 422 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK); WREG32_P 427 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK); WREG32_P 432 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_VDDC3D_OOR, SDC(s), ~SDC_MASK); WREG32_P 437 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(MPLL_TIME, MPLL_LOCK_TIME(lock_time), ~MPLL_LOCK_TIME_MASK); WREG32_P 442 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(MPLL_TIME, MPLL_RESET_TIME(reset_time), ~MPLL_RESET_TIME_MASK); WREG32_P 449 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), WREG32_P 452 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), WREG32_P 460 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), WREG32_P 463 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), WREG32_P 471 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), WREG32_P 474 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), WREG32_P 481 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), WREG32_P 488 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), WREG32_P 495 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), WREG32_P 502 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), WREG32_P 508 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK); WREG32_P 513 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(VID_RT, VID_CRTU(u), ~VID_CRTU_MASK); WREG32_P 518 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(VID_RT, VID_CRT(rt), ~VID_CRT_MASK); WREG32_P 567 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE, WREG32_P 570 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0, WREG32_P 579 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), WREG32_P 588 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), WREG32_P 597 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), WREG32_P 610 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK); WREG32_P 621 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT); WREG32_P 645 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(TARGET_AND_CURRENT_PROFILE_INDEX, DYN_PWR_ENTER_INDEX(index), WREG32_P 754 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); WREG32_P 755 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); WREG32_P 756 drivers/gpu/drm/radeon/r600_dpm.c WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); WREG32_P 186 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(acr_ctl + offset, WREG32_P 192 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_ACR_32_0 + offset, WREG32_P 195 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_ACR_32_1 + offset, WREG32_P 199 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_ACR_44_0 + offset, WREG32_P 202 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_ACR_44_1 + offset, WREG32_P 206 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_ACR_48_0 + offset, WREG32_P 209 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_ACR_48_1 + offset, WREG32_P 310 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, WREG32_P 356 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, WREG32_P 370 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, WREG32_P 383 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_60958_0 + offset, WREG32_P 388 drivers/gpu/drm/radeon/r600_hdmi.c WREG32_P(HDMI0_60958_1 + offset, WREG32_P 2549 drivers/gpu/drm/radeon/radeon.h #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) WREG32_P 2550 drivers/gpu/drm/radeon/radeon.h #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) WREG32_P 138 drivers/gpu/drm/radeon/radeon_cursor.c WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | WREG32_P 83 drivers/gpu/drm/radeon/radeon_display.c WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); WREG32_P 331 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); WREG32_P 333 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | WREG32_P 335 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); WREG32_P 347 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); WREG32_P 349 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | WREG32_P 351 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); WREG32_P 937 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CLOCK_CNTL_INDEX, WREG32_P 958 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CLOCK_CNTL_INDEX, WREG32_P 622 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32_P(RADEON_DAC_CNTL, WREG32_P 1286 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); WREG32_P 1323 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32_P(RADEON_GPIOPAD_A, 0, ~1); WREG32_P 1373 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); WREG32_P 1614 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32_P(RADEON_GPIOPAD_A, 1, ~1); WREG32_P 1670 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); WREG32_P 1028 drivers/gpu/drm/radeon/radeon_uvd.c WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); WREG32_P 1033 drivers/gpu/drm/radeon/radeon_uvd.c WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); WREG32_P 1044 drivers/gpu/drm/radeon/radeon_uvd.c WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); WREG32_P 203 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN, WREG32_P 206 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, WREG32_P 215 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), WREG32_P 218 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), WREG32_P 221 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); WREG32_P 262 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_CTRL_REG0, WREG32_P 266 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_CTRL_REG0, WREG32_P 270 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME, WREG32_P 274 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM); WREG32_P 276 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM); WREG32_P 289 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, WREG32_P 308 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE, WREG32_P 311 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_CNTRL_REG, 0, WREG32_P 318 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO); WREG32_P 320 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO); WREG32_P 340 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG2, WREG32_P 344 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_CNTRL_REG, WREG32_P 351 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE)); WREG32_P 361 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK); WREG32_P 377 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000); WREG32_P 388 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); WREG32_P 392 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_CTRL_REG0, WREG32_P 396 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_CTRL_REG0, WREG32_P 399 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0, WREG32_P 404 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); WREG32_P 414 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); WREG32_P 416 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div), WREG32_P 418 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div), WREG32_P 420 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); WREG32_P 424 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); WREG32_P 464 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG0, WREG32_P 469 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV); WREG32_P 488 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL); WREG32_P 490 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL); WREG32_P 542 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); WREG32_P 546 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, WREG32_P 549 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME); WREG32_P 552 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_CTRL_REG0, WREG32_P 556 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_PWM_CTRL_REG0, WREG32_P 562 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); WREG32_P 1066 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV); WREG32_P 317 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), WREG32_P 324 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), WREG32_P 332 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), WREG32_P 335 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), WREG32_P 342 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK); WREG32_P 348 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK); WREG32_P 355 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); WREG32_P 357 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); WREG32_P 364 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); WREG32_P 366 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); WREG32_P 373 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), WREG32_P 376 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN); WREG32_P 382 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), WREG32_P 389 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider), WREG32_P 396 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), WREG32_P 402 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(VID_RT, BRT(rt), ~BRT_MASK); WREG32_P 407 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC); WREG32_P 734 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE); WREG32_P 736 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE); WREG32_P 739 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE); WREG32_P 741 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE); WREG32_P 776 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE); WREG32_P 778 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE); WREG32_P 991 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP); WREG32_P 993 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP); WREG32_P 1173 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL, WREG32_P 1176 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, 0, WREG32_P 1212 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW), WREG32_P 1224 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW), WREG32_P 1237 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE); WREG32_P 1239 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE); WREG32_P 1258 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); WREG32_P 1260 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); WREG32_P 1267 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL); WREG32_P 1269 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL); WREG32_P 1380 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); WREG32_P 1382 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); WREG32_P 1384 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); WREG32_P 1488 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG); WREG32_P 1490 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG); WREG32_P 452 drivers/gpu/drm/radeon/rv730_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); WREG32_P 454 drivers/gpu/drm/radeon/rv730_dpm.c WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); WREG32_P 456 drivers/gpu/drm/radeon/rv730_dpm.c WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); WREG32_P 468 drivers/gpu/drm/radeon/rv730_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); WREG32_P 470 drivers/gpu/drm/radeon/rv730_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); WREG32_P 472 drivers/gpu/drm/radeon/rv730_dpm.c WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); WREG32_P 400 drivers/gpu/drm/radeon/rv740_dpm.c WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); WREG32_P 402 drivers/gpu/drm/radeon/rv740_dpm.c WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); WREG32_P 61 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 67 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); WREG32_P 82 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); WREG32_P 85 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); WREG32_P 88 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); WREG32_P 89 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); WREG32_P 96 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); WREG32_P 99 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); WREG32_P 100 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 107 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), WREG32_P 114 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); WREG32_P 119 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); WREG32_P 120 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); WREG32_P 127 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 133 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); WREG32_P 135 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P 136 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); WREG32_P 137 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); WREG32_P 176 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); WREG32_P 181 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); WREG32_P 183 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); WREG32_P 185 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); WREG32_P 197 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); WREG32_P 199 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); WREG32_P 201 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); WREG32_P 216 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); WREG32_P 218 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); WREG32_P 223 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); WREG32_P 774 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN, ~BACKBIAS_PAD_EN); WREG32_P 776 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN)); WREG32_P 786 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); WREG32_P 793 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); WREG32_P 795 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); WREG32_P 797 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); WREG32_P 841 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); WREG32_P 853 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); WREG32_P 855 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); WREG32_P 857 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); WREG32_P 859 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); WREG32_P 874 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC); WREG32_P 1336 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); WREG32_P 1338 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); WREG32_P 1365 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); WREG32_P 1367 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); WREG32_P 1586 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, SW_SMIO_INDEX(0), ~SW_SMIO_INDEX_MASK); WREG32_P 1632 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P 1633 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); WREG32_P 1634 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); WREG32_P 1638 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower), WREG32_P 1651 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_ResumeFromMinimumPower), WREG32_P 1663 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); WREG32_P 1841 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); WREG32_P 1843 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); WREG32_P 1845 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); WREG32_P 1883 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); WREG32_P 1884 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); WREG32_P 1885 drivers/gpu/drm/radeon/rv770_dpm.c WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); WREG32_P 394 drivers/gpu/drm/radeon/rv770_smc.c WREG32_P(SMC_IO, SMC_RST_N, ~SMC_RST_N); WREG32_P 399 drivers/gpu/drm/radeon/rv770_smc.c WREG32_P(SMC_IO, 0, ~SMC_RST_N); WREG32_P 404 drivers/gpu/drm/radeon/rv770_smc.c WREG32_P(SMC_IO, 0, ~SMC_CLK_EN); WREG32_P 409 drivers/gpu/drm/radeon/rv770_smc.c WREG32_P(SMC_IO, SMC_CLK_EN, ~SMC_CLK_EN); WREG32_P 433 drivers/gpu/drm/radeon/rv770_smc.c WREG32_P(SMC_MSG, HOST_SMC_MSG(msg), ~HOST_SMC_MSG_MASK); WREG32_P 6375 drivers/gpu/drm/radeon/si.c WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); WREG32_P 7003 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 7008 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); WREG32_P 7022 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); WREG32_P 7025 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); WREG32_P 7028 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); WREG32_P 7031 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); WREG32_P 7040 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); WREG32_P 7043 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); WREG32_P 7046 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); WREG32_P 7049 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); WREG32_P 7052 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9); WREG32_P 7054 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9); WREG32_P 7057 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 7065 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); WREG32_P 7070 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); WREG32_P 7077 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL_2, WREG32_P 3306 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); WREG32_P 3308 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); WREG32_P 3310 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); WREG32_P 3335 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); WREG32_P 3340 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); WREG32_P 3346 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); WREG32_P 3348 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); WREG32_P 3593 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); WREG32_P 3595 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); WREG32_P 3600 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); WREG32_P 3676 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); WREG32_P 3677 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, WREG32_P 3733 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); WREG32_P 3735 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); WREG32_P 3736 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); WREG32_P 3766 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); WREG32_P 3778 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); WREG32_P 3780 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); WREG32_P 3783 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); WREG32_P 3786 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); WREG32_P 5714 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); WREG32_P 5716 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); WREG32_P 5998 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); WREG32_P 5999 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); WREG32_P 6000 drivers/gpu/drm/radeon/si_dpm.c WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); WREG32_P 42 drivers/gpu/drm/radeon/si_smc.c WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); WREG32_P 266 drivers/gpu/drm/radeon/si_smc.c WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); WREG32_P 276 drivers/gpu/drm/radeon/si_smc.c WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); WREG32_P 91 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); WREG32_P 93 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P 94 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); WREG32_P 95 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); WREG32_P 128 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); WREG32_P 175 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u), WREG32_P 181 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u), WREG32_P 277 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); WREG32_P 279 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN); WREG32_P 436 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK); WREG32_P 437 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK); WREG32_P 441 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); WREG32_P 443 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); WREG32_P 446 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); WREG32_P 449 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); WREG32_P 480 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), WREG32_P 483 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), WREG32_P 486 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), WREG32_P 489 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), WREG32_P 565 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); WREG32_P 571 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS); WREG32_P 586 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), WREG32_P 589 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), WREG32_P 592 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), WREG32_P 595 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), WREG32_P 609 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE); WREG32_P 614 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE); WREG32_P 620 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN); WREG32_P 622 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN); WREG32_P 728 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK); WREG32_P 775 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); WREG32_P 780 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK); WREG32_P 795 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK); WREG32_P 796 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN); WREG32_P 906 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); WREG32_P 911 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK); WREG32_P 912 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK); WREG32_P 917 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET); WREG32_P 922 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET); WREG32_P 955 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN); WREG32_P 956 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN); WREG32_P 958 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN); WREG32_P 959 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN); WREG32_P 965 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK, WREG32_P 992 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1); WREG32_P 994 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1); WREG32_P 1171 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK); WREG32_P 1172 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK); WREG32_P 390 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(CG_GIPOTS, CG_GIPOT(p), ~CG_GIPOT_MASK); WREG32_P 447 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); WREG32_P 449 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P 450 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); WREG32_P 451 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); WREG32_P 462 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(seq[i], seq[i+1], ~seq[i+2]); WREG32_P 510 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); WREG32_P 512 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN); WREG32_P 763 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); WREG32_P 764 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~EN); WREG32_P 794 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(CG_CG_VOLTAGE_CNTL, EN, ~EN); WREG32_P 805 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT)); WREG32_P 810 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT, WREG32_P 1059 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK); WREG32_P 1060 drivers/gpu/drm/radeon/trinity_dpm.c WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK); WREG32_P 227 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); WREG32_P 277 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); WREG32_P 280 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); WREG32_P 281 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); WREG32_P 291 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); WREG32_P 321 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); WREG32_P 323 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); WREG32_P 342 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); WREG32_P 344 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); WREG32_P 355 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); WREG32_P 379 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); WREG32_P 397 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); WREG32_P 398 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); WREG32_P 409 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); WREG32_P 410 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); WREG32_P 222 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); WREG32_P 223 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); WREG32_P 224 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); WREG32_P 227 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); WREG32_P 230 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); WREG32_P 252 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); WREG32_P 295 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_STATUS, 1, ~1); WREG32_P 311 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); WREG32_P 313 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_SOFT_RESET, WREG32_P 321 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_SOFT_RESET, 0, ~( WREG32_P 338 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_SOFT_RESET, VCE_ECPU_SOFT_RESET, ~VCE_ECPU_SOFT_RESET); WREG32_P 340 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET); WREG32_P 346 drivers/gpu/drm/radeon/vce_v1_0.c WREG32_P(VCE_STATUS, 0, ~1); WREG32_P 162 drivers/gpu/drm/radeon/vce_v2_0.c WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); WREG32_P 163 drivers/gpu/drm/radeon/vce_v2_0.c WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); WREG32_P 164 drivers/gpu/drm/radeon/vce_v2_0.c WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); WREG32_P 168 drivers/gpu/drm/radeon/vce_v2_0.c WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); WREG32_P 190 drivers/gpu/drm/radeon/vce_v2_0.c WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); WREG32_P 192 drivers/gpu/drm/radeon/vce_v2_0.c WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, WREG32_P 1046 drivers/misc/habanalabs/habanalabs.h #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) WREG32_P 1047 drivers/misc/habanalabs/habanalabs.h #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))