WREG32_ENDPOINT    45 drivers/gpu/drm/radeon/dce3_1_afmt.c 	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
WREG32_ENDPOINT    63 drivers/gpu/drm/radeon/dce3_1_afmt.c 	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
WREG32_ENDPOINT   112 drivers/gpu/drm/radeon/dce3_1_afmt.c 		WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
WREG32_ENDPOINT   148 drivers/gpu/drm/radeon/dce6_afmt.c 	WREG32_ENDPOINT(dig->pin->offset,
WREG32_ENDPOINT   173 drivers/gpu/drm/radeon/dce6_afmt.c 	WREG32_ENDPOINT(dig->pin->offset,
WREG32_ENDPOINT   198 drivers/gpu/drm/radeon/dce6_afmt.c 	WREG32_ENDPOINT(dig->pin->offset,
WREG32_ENDPOINT   253 drivers/gpu/drm/radeon/dce6_afmt.c 		WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value);
WREG32_ENDPOINT   264 drivers/gpu/drm/radeon/dce6_afmt.c 	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
WREG32_ENDPOINT   116 drivers/gpu/drm/radeon/evergreen_hdmi.c 	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
WREG32_ENDPOINT   134 drivers/gpu/drm/radeon/evergreen_hdmi.c 	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
WREG32_ENDPOINT   152 drivers/gpu/drm/radeon/evergreen_hdmi.c 	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
WREG32_ENDPOINT   201 drivers/gpu/drm/radeon/evergreen_hdmi.c 		WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);