WREG32 1094 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(reg, tmp_); \ WREG32 1120 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) WREG32 1123 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) WREG32 147 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, WREG32 162 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdmax_gfx_context_cntl, data); WREG32 164 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, WREG32 169 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); WREG32 170 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); WREG32 171 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, WREG32 174 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); WREG32 176 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, WREG32 178 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, WREG32 181 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, WREG32 183 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, WREG32 186 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); WREG32 188 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); WREG32 189 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, WREG32 191 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, WREG32 193 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, WREG32 198 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); WREG32 268 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); WREG32 279 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); WREG32 280 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, WREG32 230 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); WREG32 231 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); WREG32 260 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, WREG32 272 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(ATHUB, 0, WREG32 279 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, WREG32 300 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), WREG32 384 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); WREG32 393 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(reg, mqd_hqd[reg - hqd_base]); WREG32 399 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); WREG32 428 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), WREG32 430 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), WREG32 432 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), WREG32 434 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), WREG32 437 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), WREG32 442 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), WREG32 447 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); WREG32 505 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, WREG32 520 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdmax_gfx_context_cntl, data); WREG32 522 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, WREG32 527 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); WREG32 528 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); WREG32 529 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, WREG32 532 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); WREG32 534 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, WREG32 536 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, WREG32 539 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, WREG32 541 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, WREG32 544 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); WREG32 546 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); WREG32 547 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, WREG32 549 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, WREG32 551 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, WREG32 556 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); WREG32 725 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); WREG32 759 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); WREG32 770 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); WREG32 771 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, WREG32 890 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); WREG32 891 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); WREG32 900 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); WREG32 929 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); WREG32 930 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); WREG32 932 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), WREG32 934 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), WREG32 937 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); WREG32 938 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); WREG32 216 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmSRBM_GFX_CNTL, value); WREG32 223 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmSRBM_GFX_CNTL, 0); WREG32 253 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmSH_MEM_CONFIG, sh_mem_config); WREG32 254 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); WREG32 255 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); WREG32 256 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmSH_MEM_BASES, sh_mem_bases); WREG32 275 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); WREG32 279 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); WREG32 282 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); WREG32 298 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | WREG32 347 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); WREG32 354 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); WREG32 364 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); WREG32 367 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmCP_HQD_ACTIVE, data); WREG32 422 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, WREG32 438 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data); WREG32 443 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data); WREG32 448 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); WREG32 449 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr); WREG32 452 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data); WREG32 454 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, WREG32 457 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, WREG32 459 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base); WREG32 460 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, WREG32 462 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, WREG32 464 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, WREG32 469 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); WREG32 556 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0); WREG32 624 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); WREG32 657 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); WREG32 668 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); WREG32 669 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, WREG32 692 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX + WREG32 711 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + WREG32 714 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + WREG32 717 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + WREG32 723 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + WREG32 738 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmGRBM_GFX_INDEX, gfx_index_val); WREG32 739 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmSQ_CMD, sq_cmd); WREG32 747 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmGRBM_GFX_INDEX, data); WREG32 787 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); WREG32 800 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, WREG32 820 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); WREG32 838 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); WREG32 172 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmSRBM_GFX_CNTL, value); WREG32 179 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmSRBM_GFX_CNTL, 0); WREG32 209 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmSH_MEM_CONFIG, sh_mem_config); WREG32 210 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); WREG32 211 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); WREG32 212 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmSH_MEM_BASES, sh_mem_bases); WREG32 232 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); WREG32 236 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); WREG32 239 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); WREG32 255 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | WREG32 311 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmRLC_CP_SCHEDULERS, value); WREG32 318 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); WREG32 326 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr); WREG32 327 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr); WREG32 328 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem); WREG32 332 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); WREG32 339 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); WREG32 349 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); WREG32 352 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmCP_HQD_ACTIVE, data); WREG32 406 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, WREG32 422 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data); WREG32 427 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data); WREG32 432 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); WREG32 433 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); WREG32 436 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data); WREG32 438 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, WREG32 441 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, WREG32 443 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); WREG32 444 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, WREG32 446 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, WREG32 448 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, WREG32 453 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); WREG32 620 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); WREG32 653 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); WREG32 664 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); WREG32 665 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, WREG32 717 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmGRBM_GFX_INDEX, gfx_index_val); WREG32 718 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmSQ_CMD, sq_cmd); WREG32 727 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmGRBM_GFX_INDEX, data); WREG32 746 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); WREG32 759 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, WREG32 779 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); WREG32 797 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); WREG32 169 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, WREG32 178 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(ATHUB, 0, WREG32 183 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, WREG32 186 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, WREG32 195 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(ATHUB, 0, WREG32 200 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, WREG32 220 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), WREG32 337 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), WREG32 404 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, WREG32 419 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdmax_gfx_context_cntl, data); WREG32 421 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, WREG32 426 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); WREG32 427 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); WREG32 428 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, WREG32 431 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); WREG32 433 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, WREG32 435 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, WREG32 438 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, WREG32 440 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, WREG32 443 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); WREG32 445 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); WREG32 446 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, WREG32 448 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, WREG32 450 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, WREG32 455 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); WREG32 597 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); WREG32 608 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); WREG32 609 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, WREG32 758 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); WREG32 1685 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch); WREG32 1706 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch); WREG32 1707 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch); WREG32 1720 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c WREG32(adev->bios_scratch_reg_offset + 3, tmp); WREG32 1887 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c WREG32(reg, val); WREG32 54 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c WREG32(offset, value); WREG32 171 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c WREG32(*pos >> 2, value); WREG32 561 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c WREG32(reg, tmp); WREG32 53 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->mask_clk_reg, temp); WREG32 58 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->a_clk_reg, temp); WREG32 61 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->a_data_reg, temp); WREG32 65 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->en_clk_reg, temp); WREG32 68 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->en_data_reg, temp); WREG32 72 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->mask_clk_reg, temp); WREG32 76 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->mask_data_reg, temp); WREG32 91 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->mask_clk_reg, temp); WREG32 95 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->mask_data_reg, temp); WREG32 140 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->en_clk_reg, val); WREG32 153 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c WREG32(rec->en_data_reg, val); WREG32 29 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h WREG32((reg), lower_32_bits(v)); \ WREG32 30 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h WREG32((reg) + 1, upper_32_bits(v)); \ WREG32 387 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); WREG32 717 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD); WREG32 66 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c WREG32(mmBIOS_SCRATCH_2, bios_2_scratch); WREG32 1988 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c WREG32(mmBIOS_SCRATCH_0, bios_0_scratch); WREG32 1989 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c WREG32(mmBIOS_SCRATCH_3, bios_3_scratch); WREG32 1990 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); WREG32 82 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmPCIE_INDEX, reg); WREG32 94 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmPCIE_INDEX, reg); WREG32 96 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmPCIE_DATA, v); WREG32 107 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmSMC_IND_INDEX_0, (reg)); WREG32 118 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmSMC_IND_INDEX_0, (reg)); WREG32 119 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmSMC_IND_DATA_0, (v)); WREG32 129 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32 140 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32 141 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmUVD_CTX_DATA, (v)); WREG32 151 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmDIDT_IND_INDEX, (reg)); WREG32 162 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmDIDT_IND_INDEX, (reg)); WREG32 163 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmDIDT_IND_DATA, (v)); WREG32 876 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); WREG32 888 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmCONFIG_CNTL, tmp); WREG32 909 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); WREG32 912 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmD1VGA_CONTROL, WREG32 915 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmD2VGA_CONTROL, WREG32 918 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmVGA_RENDER_CONTROL, WREG32 926 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmBUS_CNTL, bus_cntl); WREG32 928 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmD1VGA_CONTROL, d1vga_control); WREG32 929 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmD2VGA_CONTROL, d2vga_control); WREG32 930 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmVGA_RENDER_CONTROL, vga_render_control); WREG32 956 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); WREG32 957 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmSMC_IND_DATA_0, 0); WREG32 959 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); WREG32 1155 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute & WREG32 1157 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_MISC, save->gmcon_misc & WREG32 1167 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1168 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff); WREG32 1171 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1173 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1174 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff); WREG32 1177 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1179 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0x210000); WREG32 1180 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff); WREG32 1183 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1185 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0x21003); WREG32 1186 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff); WREG32 1189 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1191 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0x2b00); WREG32 1192 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff); WREG32 1195 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1197 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1198 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff); WREG32 1201 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1203 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0x420000); WREG32 1204 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff); WREG32 1207 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1209 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0x120202); WREG32 1210 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff); WREG32 1213 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1215 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36); WREG32 1216 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff); WREG32 1219 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1221 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e); WREG32 1222 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff); WREG32 1225 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0); WREG32 1227 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332); WREG32 1228 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff); WREG32 1230 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_MISC3, save->gmcon_misc3); WREG32 1231 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_MISC, save->gmcon_misc); WREG32 1232 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); WREG32 1727 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); WREG32 1738 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmHDP_DEBUG0, 1); WREG32 67 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_CNTL, ih_cntl); WREG32 68 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 86 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 87 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_CNTL, ih_cntl); WREG32 89 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_RPTR, 0); WREG32 90 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_WPTR, 0); WREG32 116 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); WREG32 124 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmINTERRUPT_CNTL, interrupt_cntl); WREG32 126 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); WREG32 136 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); WREG32 137 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); WREG32 139 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 142 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_RPTR, 0); WREG32 143 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_WPTR, 0); WREG32 152 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_CNTL, ih_cntl); WREG32 205 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_CNTL, tmp); WREG32 275 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_RB_RPTR, ih->rptr); WREG32 393 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 399 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 197 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], WREG32 320 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32 321 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); WREG32 382 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], WREG32 384 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], WREG32 392 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); WREG32 420 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); WREG32 448 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); WREG32 449 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); WREG32 455 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], WREG32 458 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); WREG32 459 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); WREG32 468 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32 471 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); WREG32 472 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); WREG32 473 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); WREG32 474 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); WREG32 477 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], WREG32 479 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], WREG32 484 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); WREG32 485 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); WREG32 488 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); WREG32 491 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], WREG32 499 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); WREG32 563 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); WREG32 565 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); WREG32 566 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); WREG32 888 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); WREG32 889 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); WREG32 894 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); WREG32 899 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); WREG32 912 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); WREG32 917 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); WREG32 922 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); WREG32 927 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); WREG32 1080 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); WREG32 1087 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); WREG32 1095 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1101 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1124 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); WREG32 1129 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); WREG32 1140 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); WREG32 1145 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); WREG32 67 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_CNTL, ih_cntl); WREG32 68 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 86 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 87 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_CNTL, ih_cntl); WREG32 89 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_RPTR, 0); WREG32 90 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_WPTR, 0); WREG32 116 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); WREG32 124 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmINTERRUPT_CNTL, interrupt_cntl); WREG32 127 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); WREG32 138 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); WREG32 139 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); WREG32 141 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 144 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_RPTR, 0); WREG32 145 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_WPTR, 0); WREG32 153 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_CNTL, ih_cntl); WREG32 207 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_CNTL, tmp); WREG32 254 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_RB_RPTR, ih->rptr); WREG32 372 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 378 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 181 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32 194 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32 195 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); WREG32 246 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 248 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, WREG32 251 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 254 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 318 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 350 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 356 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 365 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 395 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 448 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmVGA_HDP_CONTROL, tmp); WREG32 456 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmVGA_RENDER_CONTROL, tmp); WREG32 488 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 491 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); WREG32 492 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 571 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 624 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); WREG32 628 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); WREG32 1121 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 1125 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 1128 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 1132 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 1134 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); WREG32 1216 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); WREG32 1476 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); WREG32 1479 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); WREG32 1483 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); WREG32 1486 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); WREG32 1490 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); WREG32 1493 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); WREG32 1510 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, WREG32 1512 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, WREG32 1514 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, WREG32 1516 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, WREG32 1542 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); WREG32 1543 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); WREG32 1544 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); WREG32 1585 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ WREG32 1587 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); WREG32 1614 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); WREG32 1620 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1627 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); WREG32 1632 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); WREG32 1637 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); WREG32 1639 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ WREG32 1646 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1651 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1662 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1668 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); WREG32 1672 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); WREG32 1681 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); WREG32 1685 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, WREG32 1711 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); WREG32 1715 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); WREG32 1720 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1722 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); WREG32 1723 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); WREG32 1724 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); WREG32 1725 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); WREG32 1812 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); WREG32 1814 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); WREG32 1824 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); WREG32 1826 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); WREG32 2006 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2008 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 2010 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 2012 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 2014 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 2016 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); WREG32 2017 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); WREG32 2029 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); WREG32 2034 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); WREG32 2035 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); WREG32 2036 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); WREG32 2037 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); WREG32 2038 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32 2039 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); WREG32 2042 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); WREG32 2046 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, WREG32 2051 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, WREG32 2055 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, WREG32 2059 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); WREG32 2089 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); WREG32 2106 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2110 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2114 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2119 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2121 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); WREG32 2123 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); WREG32 2124 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); WREG32 2125 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); WREG32 2127 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2128 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2129 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2131 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); WREG32 2132 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); WREG32 2134 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); WREG32 2139 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, WREG32 2149 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2154 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2159 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2164 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2167 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); WREG32 2173 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2279 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); WREG32 2299 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 2301 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 2334 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); WREG32 2335 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); WREG32 2336 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, WREG32 2937 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 2943 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 2968 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); WREG32 2974 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); WREG32 2997 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); WREG32 3003 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); WREG32 3026 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 3031 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 3102 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], WREG32 3105 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], WREG32 3130 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], WREG32 3176 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 3191 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); WREG32 3206 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); WREG32 199 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32 212 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32 213 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); WREG32 264 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 266 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, WREG32 269 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 272 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 336 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 368 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 374 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 383 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 412 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 464 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmVGA_HDP_CONTROL, tmp); WREG32 472 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmVGA_RENDER_CONTROL, tmp); WREG32 514 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 517 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); WREG32 518 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 597 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 650 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); WREG32 654 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); WREG32 1147 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 1151 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 1154 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 1158 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 1160 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); WREG32 1242 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); WREG32 1518 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); WREG32 1521 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); WREG32 1525 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); WREG32 1528 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); WREG32 1532 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); WREG32 1535 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); WREG32 1552 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, WREG32 1554 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, WREG32 1556 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, WREG32 1558 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, WREG32 1584 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); WREG32 1585 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); WREG32 1586 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); WREG32 1627 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ WREG32 1629 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); WREG32 1656 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); WREG32 1662 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1669 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); WREG32 1674 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); WREG32 1679 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); WREG32 1681 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ WREG32 1688 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1693 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1704 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1710 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); WREG32 1714 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); WREG32 1723 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); WREG32 1727 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, WREG32 1753 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); WREG32 1757 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); WREG32 1762 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1764 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); WREG32 1765 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); WREG32 1766 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); WREG32 1767 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); WREG32 1854 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); WREG32 1856 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); WREG32 1866 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); WREG32 1868 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); WREG32 2048 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2050 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 2052 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 2054 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 2056 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 2058 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); WREG32 2059 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); WREG32 2071 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); WREG32 2076 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); WREG32 2077 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); WREG32 2078 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); WREG32 2079 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); WREG32 2080 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32 2081 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); WREG32 2084 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); WREG32 2088 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, WREG32 2093 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, WREG32 2097 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, WREG32 2101 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); WREG32 2131 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); WREG32 2147 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2151 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2155 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2157 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); WREG32 2159 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); WREG32 2160 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); WREG32 2161 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); WREG32 2163 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2164 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2165 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2167 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); WREG32 2168 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); WREG32 2170 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); WREG32 2175 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, WREG32 2185 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2189 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2193 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2197 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2200 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); WREG32 2206 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 2358 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); WREG32 2378 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 2380 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 2413 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); WREG32 2414 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); WREG32 2415 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, WREG32 3063 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 3069 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 3094 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); WREG32 3100 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); WREG32 3123 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); WREG32 3129 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); WREG32 3152 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 3157 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 3228 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], WREG32 3231 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], WREG32 3256 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], WREG32 3302 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 3317 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); WREG32 3332 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); WREG32 132 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32 145 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, WREG32 147 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); WREG32 197 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? WREG32 200 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, WREG32 203 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 205 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 269 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 294 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 305 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 337 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); WREG32 352 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmVGA_RENDER_CONTROL, WREG32 385 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 388 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); WREG32 389 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 449 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 956 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); WREG32 957 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, WREG32 964 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); WREG32 965 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, WREG32 969 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); WREG32 972 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); WREG32 973 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); WREG32 1017 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, WREG32 1020 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, WREG32 1119 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, WREG32 1387 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1404 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1408 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); WREG32 1411 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); WREG32 1415 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); WREG32 1418 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); WREG32 1422 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); WREG32 1425 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); WREG32 1455 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, WREG32 1457 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, WREG32 1459 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, WREG32 1461 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, WREG32 1468 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); WREG32 1495 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); WREG32 1497 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); WREG32 1498 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock); WREG32 1500 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); WREG32 1501 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock); WREG32 1515 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); WREG32 1519 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); WREG32 1523 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); WREG32 1532 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); WREG32 1536 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); WREG32 1541 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1546 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1559 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_GC + dig->afmt->offset, tmp); WREG32 1576 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); WREG32 1580 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); WREG32 1584 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1591 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); WREG32 1595 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1610 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); WREG32 1614 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); WREG32 1621 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); WREG32 1623 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); WREG32 1775 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); WREG32 1784 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); WREG32 1944 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); WREG32 1946 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 1948 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 1950 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 1952 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 1954 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); WREG32 1955 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); WREG32 1969 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); WREG32 1970 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); WREG32 1971 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); WREG32 1972 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); WREG32 1973 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32 1974 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); WREG32 1977 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); WREG32 1981 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, WREG32 1985 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, WREG32 1990 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, WREG32 1994 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); WREG32 2020 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, WREG32 2023 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); WREG32 2037 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2040 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2042 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2044 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2048 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); WREG32 2050 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); WREG32 2051 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); WREG32 2052 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); WREG32 2054 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2055 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2056 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2058 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); WREG32 2059 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); WREG32 2061 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); WREG32 2066 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, WREG32 2072 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2077 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2080 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2083 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2087 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); WREG32 2169 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); WREG32 2189 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 2191 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 2227 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); WREG32 2228 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); WREG32 2229 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, WREG32 2831 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmINT_MASK + reg_block, interrupt_mask); WREG32 2836 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmINT_MASK + reg_block, interrupt_mask); WREG32 2866 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); WREG32 2871 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); WREG32 2940 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); WREG32 2951 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); WREG32 2979 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], WREG32 2982 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], WREG32 3007 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], WREG32 3060 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 129 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32 142 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32 143 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); WREG32 190 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? WREG32 193 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, WREG32 196 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 199 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 263 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 288 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 299 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); WREG32 330 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); WREG32 381 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmVGA_HDP_CONTROL, tmp); WREG32 389 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmVGA_RENDER_CONTROL, tmp); WREG32 428 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 431 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); WREG32 432 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 508 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 559 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, WREG32 563 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, WREG32 1058 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 1059 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, WREG32 1066 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); WREG32 1067 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, WREG32 1071 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); WREG32 1153 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset, WREG32 1437 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT)); WREG32 1438 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz); WREG32 1440 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); WREG32 1441 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz); WREG32 1443 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); WREG32 1444 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz); WREG32 1461 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_AVI_INFO0 + offset, WREG32 1463 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_AVI_INFO1 + offset, WREG32 1465 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_AVI_INFO2 + offset, WREG32 1467 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_AVI_INFO3 + offset, WREG32 1489 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT)); WREG32 1490 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); WREG32 1491 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); WREG32 1532 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, WREG32 1535 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000); WREG32 1564 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_CONTROL + offset, val); WREG32 1566 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, WREG32 1571 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset, WREG32 1575 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset, WREG32 1578 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset, WREG32 1581 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ WREG32 1583 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset, WREG32 1587 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset, WREG32 1593 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, WREG32 1596 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, WREG32 1602 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_60958_0 + offset, WREG32 1605 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_60958_1 + offset, WREG32 1608 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_60958_2 + offset, WREG32 1619 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset, WREG32 1651 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); WREG32 1652 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); WREG32 1653 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001); WREG32 1654 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001); WREG32 1741 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); WREG32 1743 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); WREG32 1753 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); WREG32 1755 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); WREG32 1918 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); WREG32 1920 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 1922 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 1924 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 1926 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 1928 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); WREG32 1929 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); WREG32 1943 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); WREG32 1944 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); WREG32 1945 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); WREG32 1946 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); WREG32 1947 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32 1948 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); WREG32 1951 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); WREG32 1955 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, WREG32 1960 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, WREG32 1964 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, WREG32 1968 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); WREG32 1993 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, WREG32 1996 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); WREG32 2009 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2012 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2014 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2016 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2020 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); WREG32 2022 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); WREG32 2023 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); WREG32 2024 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); WREG32 2026 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2027 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2028 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); WREG32 2030 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); WREG32 2031 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); WREG32 2033 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); WREG32 2038 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, WREG32 2044 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2048 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2051 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2054 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2058 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); WREG32 2062 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, WREG32 2182 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); WREG32 2200 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, WREG32 2202 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, WREG32 2235 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); WREG32 2236 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); WREG32 2237 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, WREG32 2825 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 2831 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 2879 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); WREG32 2884 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); WREG32 2930 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); WREG32 2935 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); WREG32 2958 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); WREG32 2963 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); WREG32 3032 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); WREG32 3043 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); WREG32 3071 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], WREG32 3074 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], WREG32 3099 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], WREG32 3152 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); WREG32 106 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); WREG32 107 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(data, ficaa_val); WREG32 109 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3); WREG32 112 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); WREG32 129 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); WREG32 130 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(data, ficaa_val); WREG32 132 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3); WREG32 133 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(data, ficadl_val); WREG32 135 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); WREG32 136 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(data, ficadh_val); WREG32 157 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(address, lo_addr); WREG32 159 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(address, hi_addr); WREG32 179 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(address, lo_addr); WREG32 180 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(data, lo_val); WREG32 181 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(address, hi_addr); WREG32 182 drivers/gpu/drm/amd/amdgpu/df_v3_6.c WREG32(data, hi_val); WREG32 447 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32(scratch, 0xCAFEDEAD); WREG32 503 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32(scratch, 0xCAFEDEAD); WREG32 1893 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); WREG32 4882 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32(cp_int_cntl_reg, cp_int_cntl); WREG32 4888 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32(cp_int_cntl_reg, cp_int_cntl); WREG32 4935 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32(mec_int_cntl_reg, mec_int_cntl); WREG32 4941 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32(mec_int_cntl_reg, mec_int_cntl); WREG32 5139 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32(target, tmp); WREG32 5149 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32(target, tmp); WREG32 641 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); WREG32 847 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); WREG32 1071 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); WREG32 1295 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); WREG32 1323 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGRBM_GFX_INDEX, data); WREG32 1456 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); WREG32 1495 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmPA_SC_RASTER_CONFIG, raster_config); WREG32 1528 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); WREG32 1561 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); WREG32 1675 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); WREG32 1676 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSRBM_INT_CNTL, 1); WREG32 1677 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSRBM_INT_ACK, 1); WREG32 1679 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); WREG32 1713 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmGB_ADDR_CONFIG, gb_addr_config); WREG32 1714 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); WREG32 1715 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmDMIF_ADDR_CALC, gb_addr_config); WREG32 1716 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); WREG32 1717 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); WREG32 1718 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); WREG32 1722 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); WREG32 1723 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); WREG32 1724 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); WREG32 1736 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | WREG32 1738 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | WREG32 1742 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSX_DEBUG_1, sx_debug_1); WREG32 1744 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); WREG32 1746 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | WREG32 1751 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmVGT_NUM_INSTANCES, 1); WREG32 1752 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_PERFMON_CNTL, 0); WREG32 1753 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSQ_CONFIG, 0); WREG32 1754 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | WREG32 1757 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmVGT_CACHE_INVALIDATION, WREG32 1761 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmVGT_GS_VERTEX_REUSE, 16); WREG32 1762 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); WREG32 1764 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); WREG32 1765 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); WREG32 1766 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); WREG32 1767 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); WREG32 1768 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); WREG32 1769 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); WREG32 1770 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); WREG32 1771 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); WREG32 1774 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); WREG32 1776 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | WREG32 1802 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(scratch, 0xCAFEDEAD); WREG32 1916 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(scratch, 0xCAFEDEAD); WREG32 1956 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_ME_CNTL, 0); WREG32 1958 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | WREG32 1961 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSCRATCH_UMSK, 0); WREG32 1995 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_PFP_UCODE_ADDR, 0); WREG32 1997 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 1998 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_PFP_UCODE_ADDR, 0); WREG32 2004 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_CE_UCODE_ADDR, 0); WREG32 2006 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 2007 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_CE_UCODE_ADDR, 0); WREG32 2013 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_ME_RAM_WADDR, 0); WREG32 2015 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); WREG32 2016 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_ME_RAM_WADDR, 0); WREG32 2018 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_PFP_UCODE_ADDR, 0); WREG32 2019 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_CE_UCODE_ADDR, 0); WREG32 2020 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_ME_RAM_WADDR, 0); WREG32 2021 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_ME_RAM_RADDR, 0); WREG32 2098 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_SEM_WAIT_TIMER, 0x0); WREG32 2099 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); WREG32 2102 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB_WPTR_DELAY, 0); WREG32 2104 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_DEBUG, 0); WREG32 2105 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSCRATCH_ADDR, 0); WREG32 2116 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_CNTL, tmp); WREG32 2119 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); WREG32 2121 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_WPTR, ring->wptr); WREG32 2125 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); WREG32 2126 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); WREG32 2128 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSCRATCH_UMSK, 0); WREG32 2131 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_CNTL, tmp); WREG32 2133 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); WREG32 2167 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); WREG32 2176 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); WREG32 2179 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); WREG32 2204 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_CNTL, tmp); WREG32 2206 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); WREG32 2208 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_WPTR, ring->wptr); WREG32 2211 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); WREG32 2212 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); WREG32 2215 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_CNTL, tmp); WREG32 2216 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); WREG32 2224 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_CNTL, tmp); WREG32 2226 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); WREG32 2228 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_WPTR, ring->wptr); WREG32 2230 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); WREG32 2231 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); WREG32 2234 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_CNTL, tmp); WREG32 2235 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); WREG32 2270 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING0, tmp); WREG32 2436 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSPI_LB_CU_MASK, 0x00ff); WREG32 2463 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CNTL, rlc); WREG32 2474 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CNTL, data); WREG32 2484 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CNTL, 0); WREG32 2492 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); WREG32 2538 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_RL_BASE, 0); WREG32 2539 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_RL_SIZE, 0); WREG32 2540 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_LB_CNTL, 0); WREG32 2541 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); WREG32 2542 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_LB_CNTR_INIT, 0); WREG32 2543 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); WREG32 2545 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_MC_CNTL, 0); WREG32 2546 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_UCODE_CNTL, 0); WREG32 2556 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_UCODE_ADDR, i); WREG32 2557 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 2559 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_UCODE_ADDR, 0); WREG32 2576 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); WREG32 2580 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); WREG32 2581 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); WREG32 2582 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); WREG32 2587 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); WREG32 2602 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CGCG_CGLS_CTRL, data); WREG32 2615 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCGTS_SM_CTRL_REG, data); WREG32 2621 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_MEM_SLP_CNTL, data); WREG32 2627 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); WREG32 2631 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); WREG32 2632 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); WREG32 2633 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); WREG32 2640 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); WREG32 2645 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_MEM_SLP_CNTL, data); WREG32 2650 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCGTS_SM_CTRL_REG, data); WREG32 2654 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); WREG32 2655 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); WREG32 2656 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); WREG32 2697 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 2775 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); WREG32 2788 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); WREG32 2793 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_MAX_PG_CU, tmp); WREG32 2807 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 2821 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 2828 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); WREG32 2830 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); WREG32 2836 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_AUTO_PG_CTRL, tmp); WREG32 2936 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); WREG32 2937 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); WREG32 2944 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); WREG32 2945 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); WREG32 2970 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); WREG32 2989 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSQ_IND_INDEX, WREG32 3001 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmSQ_IND_INDEX, WREG32 3245 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 3250 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 3267 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); WREG32 3272 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); WREG32 3280 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); WREG32 3285 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); WREG32 3308 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 3313 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 3333 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 3338 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 1216 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); WREG32 1219 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); WREG32 1399 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); WREG32 1402 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); WREG32 1569 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); WREG32 1572 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); WREG32 1610 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGRBM_GFX_INDEX, data); WREG32 1770 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); WREG32 1771 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); WREG32 1818 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmPA_SC_RASTER_CONFIG, raster_config); WREG32 1819 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); WREG32 1875 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSH_MEM_CONFIG, sh_mem_config); WREG32 1876 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSH_MEM_APE1_BASE, 1); WREG32 1877 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSH_MEM_APE1_LIMIT, 0); WREG32 1878 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSH_MEM_BASES, sh_mem_bases); WREG32 1886 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); WREG32 1887 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); WREG32 1888 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(amdgpu_gds_reg_offset[i].gws, 0); WREG32 1889 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(amdgpu_gds_reg_offset[i].oa, 0); WREG32 1904 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); WREG32 1905 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); WREG32 1906 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); WREG32 1907 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); WREG32 1930 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); WREG32 1932 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 1933 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 1934 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); WREG32 1943 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEQ_THRESHOLDS, WREG32 1970 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); WREG32 1980 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); WREG32 1981 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSH_MEM_APE1_BASE, 1); WREG32 1982 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSH_MEM_APE1_LIMIT, 0); WREG32 1983 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSH_MEM_BASES, sh_mem_base); WREG32 1991 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSX_DEBUG_1, 0x20); WREG32 1993 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmTA_CNTL_AUX, 0x00010000); WREG32 1997 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSPI_CONFIG_CNTL, tmp); WREG32 1999 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSQ_CONFIG, 1); WREG32 2001 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmDB_DEBUG, 0); WREG32 2005 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmDB_DEBUG2, tmp); WREG32 2009 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmDB_DEBUG3, tmp); WREG32 2013 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCB_HW_CONTROL, tmp); WREG32 2015 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); WREG32 2017 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmPA_SC_FIFO_SIZE, WREG32 2023 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmVGT_NUM_INSTANCES, 1); WREG32 2025 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_PERFMON_CNTL, 0); WREG32 2027 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSQ_CONFIG, 0); WREG32 2029 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, WREG32 2033 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmVGT_CACHE_INVALIDATION, WREG32 2037 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmVGT_GS_VERTEX_REUSE, 16); WREG32 2038 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); WREG32 2040 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | WREG32 2042 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); WREG32 2049 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSPI_ARB_PRIORITY, tmp); WREG32 2099 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(scratch, 0xCAFEDEAD); WREG32 2365 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(scratch, 0xCAFEDEAD); WREG32 2437 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_ME_CNTL, 0); WREG32 2439 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK)); WREG32 2486 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_PFP_UCODE_ADDR, 0); WREG32 2488 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 2489 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); WREG32 2496 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_CE_UCODE_ADDR, 0); WREG32 2498 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 2499 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); WREG32 2506 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_ME_RAM_WADDR, 0); WREG32 2508 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); WREG32 2509 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); WREG32 2531 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); WREG32 2532 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_ENDIAN_SWAP, 0); WREG32 2533 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_DEVICE_ID, 1); WREG32 2607 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_SEM_WAIT_TIMER, 0x0); WREG32 2609 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); WREG32 2612 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB_WPTR_DELAY, 0); WREG32 2615 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB_VMID, 0); WREG32 2617 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSCRATCH_ADDR, 0); WREG32 2627 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_CNTL, tmp); WREG32 2630 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); WREG32 2632 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); WREG32 2636 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); WREG32 2637 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); WREG32 2640 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSCRATCH_UMSK, 0); WREG32 2643 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_CNTL, tmp); WREG32 2646 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_BASE, rb_addr); WREG32 2647 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); WREG32 2674 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); WREG32 2706 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEC_CNTL, 0); WREG32 2708 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); WREG32 2745 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); WREG32 2747 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 2748 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); WREG32 2767 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); WREG32 2769 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 2770 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); WREG32 2888 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); WREG32 2889 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); WREG32 2892 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_HPD_EOP_VMID, 0); WREG32 2898 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_HPD_EOP_CONTROL, tmp); WREG32 2910 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); WREG32 2920 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); WREG32 2921 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_HQD_PQ_RPTR, 0); WREG32 2922 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_HQD_PQ_WPTR, 0); WREG32 3060 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); WREG32 3064 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); WREG32 3068 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); WREG32 3121 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_CPF_DEBUG, tmp); WREG32 3178 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_INT_CNTL_RING0, tmp); WREG32 3361 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_LB_CNTL, tmp); WREG32 3400 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_CNTL, rlc); WREG32 3413 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_CNTL, data); WREG32 3437 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPR_REG2, tmp); WREG32 3459 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPR_REG2, tmp); WREG32 3471 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_CNTL, 0); WREG32 3487 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); WREG32 3499 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGRBM_SOFT_RESET, tmp); WREG32 3502 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGRBM_SOFT_RESET, tmp); WREG32 3535 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); WREG32 3541 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_LB_CNTR_INIT, 0); WREG32 3542 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); WREG32 3546 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); WREG32 3547 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_LB_PARAMS, 0x00600408); WREG32 3548 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_LB_CNTL, 0x80000004); WREG32 3551 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_MC_CNTL, 0); WREG32 3552 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_UCODE_CNTL, 0); WREG32 3557 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_UCODE_ADDR, 0); WREG32 3559 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 3560 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); WREG32 3566 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); WREG32 3586 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); WREG32 3587 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); WREG32 3591 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_SERDES_WR_CTRL, tmp2); WREG32 3598 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_CGCG_CGLS_CTRL, data); WREG32 3610 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_CGCG_CGLS_CTRL, data); WREG32 3626 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEM_SLP_CNTL, data); WREG32 3634 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); WREG32 3640 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); WREG32 3641 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); WREG32 3644 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_SERDES_WR_CTRL, data); WREG32 3662 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCGTS_SM_CTRL_REG, data); WREG32 3668 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); WREG32 3673 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_MEM_SLP_CNTL, data); WREG32 3679 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEM_SLP_CNTL, data); WREG32 3685 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCGTS_SM_CTRL_REG, data); WREG32 3691 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); WREG32 3692 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); WREG32 3694 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_SERDES_WR_CTRL, data); WREG32 3727 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 3741 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 3754 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 3767 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 3787 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 3792 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_AUTO_PG_CTRL, data); WREG32 3797 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 3802 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_AUTO_PG_CTRL, data); WREG32 3819 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); WREG32 3841 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); WREG32 3846 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_MAX_PG_CU, tmp); WREG32 3860 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 3874 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 3886 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); WREG32 3887 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); WREG32 3888 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); WREG32 3889 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); WREG32 3891 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); WREG32 3893 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_SCRATCH_DATA, 0); WREG32 3896 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); WREG32 3898 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); WREG32 3904 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_CNTL, data); WREG32 3906 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); WREG32 3907 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); WREG32 3912 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB_WPTR_POLL_CNTL, data); WREG32 3915 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_DELAY, data); WREG32 3920 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_PG_DELAY_2, data); WREG32 3925 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_AUTO_PG_CTRL, data); WREG32 4083 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); WREG32 4138 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSQ_CMD, value); WREG32 4143 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSQ_IND_INDEX, WREG32 4155 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSQ_IND_INDEX, WREG32 4664 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); WREG32 4667 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); WREG32 4673 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGRBM_SOFT_RESET, tmp); WREG32 4679 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmGRBM_SOFT_RESET, tmp); WREG32 4687 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 4693 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 4711 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 4716 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 4762 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mec_int_cntl_reg, mec_int_cntl); WREG32 4767 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mec_int_cntl_reg, mec_int_cntl); WREG32 4785 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 4790 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 4810 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 4815 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); WREG32 848 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(scratch, 0xCAFEDEAD); WREG32 1566 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_EDC_MODE, 0); WREG32 1692 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_EDC_MODE, tmp); WREG32 1696 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCC_GC_EDC_CONFIG, tmp); WREG32 2306 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); WREG32 2310 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); WREG32 2496 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); WREG32 2500 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); WREG32 2685 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); WREG32 2689 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); WREG32 2888 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); WREG32 2892 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); WREG32 3090 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); WREG32 3094 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); WREG32 3261 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); WREG32 3265 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); WREG32 3438 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); WREG32 3442 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); WREG32 3468 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGRBM_GFX_INDEX, data); WREG32 3634 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); WREG32 3635 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); WREG32 3673 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmPA_SC_RASTER_CONFIG, raster_config); WREG32 3674 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); WREG32 3735 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_MEM_CONFIG, sh_mem_config); WREG32 3736 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_MEM_APE1_BASE, 1); WREG32 3737 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_MEM_APE1_LIMIT, 0); WREG32 3738 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_MEM_BASES, sh_mem_bases); WREG32 3746 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); WREG32 3747 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); WREG32 3748 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(amdgpu_gds_reg_offset[i].gws, 0); WREG32 3749 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(amdgpu_gds_reg_offset[i].oa, 0); WREG32 3764 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); WREG32 3765 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); WREG32 3766 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); WREG32 3767 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); WREG32 3790 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 3791 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 3792 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); WREG32 3807 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); WREG32 3818 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_MEM_CONFIG, tmp); WREG32 3819 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_MEM_BASES, 0); WREG32 3825 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_MEM_CONFIG, tmp); WREG32 3827 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_MEM_BASES, tmp); WREG32 3830 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_MEM_APE1_BASE, 1); WREG32 3831 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSH_MEM_APE1_LIMIT, 0); WREG32 3846 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmPA_SC_FIFO_SIZE, WREG32 3861 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSPI_ARB_PRIORITY, tmp); WREG32 3915 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_INT_CNTL_RING0, tmp); WREG32 3921 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CSIB_ADDR_HI, WREG32 3923 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CSIB_ADDR_LO, WREG32 3925 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CSIB_LENGTH, WREG32 4007 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_SRM_ARAM_ADDR, 0); WREG32 4009 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); WREG32 4012 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); WREG32 4014 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]); WREG32 4018 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); WREG32 4019 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_GPM_SCRATCH_DATA, list_size); WREG32 4022 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_GPM_SCRATCH_ADDR, WREG32 4025 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_GPM_SCRATCH_DATA, WREG32 4033 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(temp + i, unique_indices[i] & 0x3FFFF); WREG32 4034 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(data + i, unique_indices[i] >> 20); WREG32 4057 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_PG_DELAY, data); WREG32 4088 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); WREG32 4090 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); WREG32 4161 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_ME_CNTL, tmp); WREG32 4202 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); WREG32 4203 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_ENDIAN_SWAP, 0); WREG32 4204 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_DEVICE_ID, 1); WREG32 4277 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB_DOORBELL_CONTROL, tmp); WREG32 4285 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp); WREG32 4287 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB_DOORBELL_RANGE_UPPER, WREG32 4299 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB_WPTR_DELAY, 0); WREG32 4302 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB_VMID, 0); WREG32 4314 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_CNTL, tmp); WREG32 4317 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); WREG32 4319 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); WREG32 4323 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); WREG32 4324 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); WREG32 4327 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); WREG32 4328 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); WREG32 4330 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_CNTL, tmp); WREG32 4333 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_BASE, rb_addr); WREG32 4334 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); WREG32 4350 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_MEC_CNTL, 0); WREG32 4352 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); WREG32 4370 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CP_SCHEDULERS, tmp); WREG32 4372 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CP_SCHEDULERS, tmp); WREG32 4450 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); WREG32 4451 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_HQD_PQ_RPTR, 0); WREG32 4452 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_HQD_PQ_WPTR, 0); WREG32 4614 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); WREG32 4622 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr); WREG32 4623 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr); WREG32 4624 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem); WREG32 4628 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); WREG32 4632 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); WREG32 4710 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2); WREG32 4711 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2); WREG32 5096 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGMCON_DEBUG, tmp); WREG32 5104 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGRBM_SOFT_RESET, tmp); WREG32 5110 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGRBM_SOFT_RESET, tmp); WREG32 5118 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 5124 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 5132 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGMCON_DEBUG, tmp); WREG32 5195 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); WREG32 5243 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSQ_IND_INDEX, WREG32 5255 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSQ_IND_INDEX, WREG32 5532 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); WREG32 5533 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); WREG32 5563 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_SERDES_WR_CTRL, data); WREG32 5592 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_SAFE_MODE, data); WREG32 5619 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_SAFE_MODE, data); WREG32 5673 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); WREG32 5694 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCGTS_SM_CTRL_REG, data); WREG32 5708 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); WREG32 5714 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_MEM_SLP_CNTL, data); WREG32 5721 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_MEM_SLP_CNTL, data); WREG32 5729 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCGTS_SM_CTRL_REG, data); WREG32 5759 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); WREG32 5784 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); WREG32 5790 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CGCG_CGLS_CTRL, data); WREG32 5805 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); WREG32 5829 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmRLC_CGCG_CGLS_CTRL, data); WREG32 6066 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); WREG32 6291 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(reg, tmp); WREG32 6354 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_HQD_PIPE_PRIORITY, pipe_priority); WREG32 6355 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_HQD_QUEUE_PRIORITY, queue_priority); WREG32 6534 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmSQ_CMD, value); WREG32 6583 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mec_int_cntl_reg, mec_int_cntl); WREG32 6588 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mec_int_cntl_reg, mec_int_cntl); WREG32 7113 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); WREG32 851 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(scratch, 0xCAFEDEAD); WREG32 2677 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); WREG32 2680 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), WREG32 2683 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), WREG32 2687 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), WREG32 2692 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), WREG32 2720 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), WREG32 2722 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); WREG32 2725 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), WREG32 2728 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), WREG32 2734 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) WREG32 2738 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) WREG32 2764 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); WREG32 2770 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); WREG32 2775 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); WREG32 2790 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); WREG32 2798 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); WREG32 2803 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); WREG32 2808 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); WREG32 2815 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); WREG32 2832 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); WREG32 2846 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); WREG32 2860 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); WREG32 2873 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); WREG32 2886 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); WREG32 2903 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); WREG32 2916 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); WREG32 2941 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(mmRLC_JUMP_TABLE_RESTORE, WREG32 5170 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(reg, tmp); WREG32 5534 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(mec_int_cntl_reg, mec_int_cntl); WREG32 5540 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(mec_int_cntl_reg, mec_int_cntl); WREG32 89 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c WREG32(reg, tmp); WREG32 98 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c WREG32(reg, tmp); WREG32 108 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c WREG32(reg, tmp); WREG32 117 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c WREG32(reg, tmp); WREG32 84 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmBIF_FB_EN, 0); WREG32 88 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); WREG32 102 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); WREG32 106 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmBIF_FB_EN, tmp); WREG32 190 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); WREG32 191 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); WREG32 195 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); WREG32 196 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); WREG32 200 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); WREG32 204 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); WREG32 205 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); WREG32 206 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); WREG32 241 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32((0xb05 + j), 0x00000000); WREG32 242 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32((0xb06 + j), 0x00000000); WREG32 243 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32((0xb07 + j), 0x00000000); WREG32 244 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32((0xb08 + j), 0x00000000); WREG32 245 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32((0xb09 + j), 0x00000000); WREG32 247 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); WREG32 259 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVGA_HDP_CONTROL, tmp); WREG32 264 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVGA_RENDER_CONTROL, tmp); WREG32 267 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 269 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 271 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, WREG32 273 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_VM_AGP_BASE, 0); WREG32 274 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); WREG32 275 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); WREG32 368 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); WREG32 428 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 459 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_CNTL, tmp); WREG32 466 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); WREG32 467 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); WREG32 468 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); WREG32 469 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); WREG32 470 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); WREG32 471 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); WREG32 472 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); WREG32 473 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); WREG32 475 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); WREG32 476 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); WREG32 477 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); WREG32 478 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); WREG32 479 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); WREG32 480 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); WREG32 481 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); WREG32 482 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); WREG32 503 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_VM_MX_L1_TLB_CNTL, WREG32 511 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_L2_CNTL, WREG32 518 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_L2_CNTL2, WREG32 523 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_L2_CNTL3, WREG32 528 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); WREG32 529 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); WREG32 530 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); WREG32 531 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 533 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT0_CNTL2, 0); WREG32 534 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT0_CNTL, WREG32 539 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(0x575, 0); WREG32 540 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(0x576, 0); WREG32 541 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(0x577, 0); WREG32 545 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); WREG32 546 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); WREG32 553 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, WREG32 556 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, WREG32 561 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 563 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT1_CNTL2, 4); WREG32 564 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT1_CNTL, WREG32 612 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT0_CNTL, 0); WREG32 613 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT1_CNTL, 0); WREG32 615 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmMC_VM_MX_L1_TLB_CNTL, WREG32 619 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_L2_CNTL, WREG32 624 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_L2_CNTL2, 0); WREG32 625 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_L2_CNTL3, WREG32 1038 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1044 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1073 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT0_CNTL, tmp); WREG32 1076 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 1081 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT0_CNTL, tmp); WREG32 1084 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 99 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmBIF_FB_EN, 0); WREG32 103 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); WREG32 116 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); WREG32 120 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmBIF_FB_EN, tmp); WREG32 207 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); WREG32 208 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); WREG32 212 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); WREG32 213 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); WREG32 217 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); WREG32 220 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); WREG32 221 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); WREG32 222 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); WREG32 267 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32((0xb05 + j), 0x00000000); WREG32 268 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32((0xb06 + j), 0x00000000); WREG32 269 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32((0xb07 + j), 0x00000000); WREG32 270 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32((0xb08 + j), 0x00000000); WREG32 271 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32((0xb09 + j), 0x00000000); WREG32 273 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); WREG32 282 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVGA_HDP_CONTROL, tmp); WREG32 287 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVGA_RENDER_CONTROL, tmp); WREG32 290 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 292 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 294 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, WREG32 296 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_VM_AGP_BASE, 0); WREG32 297 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); WREG32 298 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); WREG32 303 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); WREG32 307 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmHDP_MISC_CNTL, tmp); WREG32 310 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmHDP_HOST_PATH_CNTL, tmp); WREG32 440 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); WREG32 511 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 544 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_CNTL, tmp); WREG32 551 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); WREG32 552 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); WREG32 553 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); WREG32 554 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); WREG32 555 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); WREG32 556 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); WREG32 557 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); WREG32 558 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); WREG32 560 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); WREG32 561 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); WREG32 562 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); WREG32 563 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); WREG32 564 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); WREG32 565 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); WREG32 566 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); WREG32 567 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); WREG32 605 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); WREG32 615 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_L2_CNTL, tmp); WREG32 618 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_L2_CNTL2, tmp); WREG32 625 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_L2_CNTL3, tmp); WREG32 627 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); WREG32 628 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); WREG32 629 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); WREG32 630 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 632 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT0_CNTL2, 0); WREG32 637 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT0_CNTL, tmp); WREG32 639 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(0x575, 0); WREG32 640 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(0x576, 0); WREG32 641 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(0x577, 0); WREG32 648 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); WREG32 649 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); WREG32 652 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, WREG32 655 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, WREG32 660 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 662 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT1_CNTL2, 4); WREG32 668 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 677 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmCHUB_CONTROL, tmp); WREG32 717 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT0_CNTL, 0); WREG32 718 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT1_CNTL, 0); WREG32 724 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); WREG32 728 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_L2_CNTL, tmp); WREG32 729 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_L2_CNTL2, 0); WREG32 812 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mc_cg_registers[i], data); WREG32 829 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mc_cg_registers[i], data); WREG32 869 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmHDP_HOST_PATH_CNTL, data); WREG32 885 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmHDP_MEM_POWER_LS, data); WREG32 1183 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1189 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1220 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT0_CNTL, tmp); WREG32 1224 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 1230 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT0_CNTL, tmp); WREG32 1234 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 187 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmBIF_FB_EN, 0); WREG32 191 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); WREG32 204 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); WREG32 208 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmBIF_FB_EN, tmp); WREG32 332 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); WREG32 333 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); WREG32 337 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); WREG32 338 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); WREG32 342 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); WREG32 345 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); WREG32 346 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); WREG32 347 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); WREG32 399 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_MISC0, data); WREG32 403 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); WREG32 404 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); WREG32 407 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); WREG32 408 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); WREG32 412 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); WREG32 415 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); WREG32 416 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); WREG32 417 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); WREG32 458 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32((0xb05 + j), 0x00000000); WREG32 459 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32((0xb06 + j), 0x00000000); WREG32 460 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32((0xb07 + j), 0x00000000); WREG32 461 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32((0xb08 + j), 0x00000000); WREG32 462 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32((0xb09 + j), 0x00000000); WREG32 464 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); WREG32 473 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVGA_HDP_CONTROL, tmp); WREG32 478 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVGA_RENDER_CONTROL, tmp); WREG32 481 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 483 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 485 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, WREG32 491 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_VM_FB_LOCATION, tmp); WREG32 493 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); WREG32 494 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); WREG32 495 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); WREG32 498 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_VM_AGP_BASE, 0); WREG32 499 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); WREG32 500 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); WREG32 505 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); WREG32 509 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmHDP_MISC_CNTL, tmp); WREG32 512 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmHDP_HOST_PATH_CNTL, tmp); WREG32 642 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); WREG32 738 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 771 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_CNTL, tmp); WREG32 778 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); WREG32 779 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); WREG32 780 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); WREG32 781 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); WREG32 782 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); WREG32 783 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); WREG32 784 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); WREG32 785 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); WREG32 787 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); WREG32 788 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); WREG32 789 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); WREG32 790 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); WREG32 791 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); WREG32 792 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); WREG32 793 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); WREG32 794 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); WREG32 832 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); WREG32 842 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CNTL, tmp); WREG32 846 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CNTL2, tmp); WREG32 853 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CNTL3, tmp); WREG32 868 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CNTL4, tmp); WREG32 870 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); WREG32 871 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); WREG32 872 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); WREG32 873 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 875 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT0_CNTL2, 0); WREG32 880 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT0_CNTL, tmp); WREG32 882 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); WREG32 883 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); WREG32 884 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); WREG32 891 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); WREG32 892 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); WREG32 895 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, WREG32 898 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, WREG32 903 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 905 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT1_CNTL2, 4); WREG32 918 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 961 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT0_CNTL, 0); WREG32 962 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT1_CNTL, 0); WREG32 968 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); WREG32 972 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CNTL, tmp); WREG32 973 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CNTL2, 0); WREG32 1346 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1352 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1392 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT0_CNTL, tmp); WREG32 1396 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 1402 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT0_CNTL, tmp); WREG32 1406 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_CONTEXT1_CNTL, tmp); WREG32 1491 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_HUB_CG, data); WREG32 1495 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_SIP_CG, data); WREG32 1499 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_VM_CG, data); WREG32 1503 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_XPB_CLK_GAT, data); WREG32 1507 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmATC_MISC_CG, data); WREG32 1511 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_WR_CG, data); WREG32 1515 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_RD_CG, data); WREG32 1519 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_VM_CG, data); WREG32 1523 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CG, data); WREG32 1527 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_HUB_CG, data); WREG32 1531 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_SIP_CG, data); WREG32 1535 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_VM_CG, data); WREG32 1539 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_XPB_CLK_GAT, data); WREG32 1543 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmATC_MISC_CG, data); WREG32 1547 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_WR_CG, data); WREG32 1551 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_RD_CG, data); WREG32 1555 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_VM_CG, data); WREG32 1559 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CG, data); WREG32 1571 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_HUB_CG, data); WREG32 1575 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_SIP_CG, data); WREG32 1579 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_VM_CG, data); WREG32 1583 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_XPB_CLK_GAT, data); WREG32 1587 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmATC_MISC_CG, data); WREG32 1591 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_WR_CG, data); WREG32 1595 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_RD_CG, data); WREG32 1599 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_VM_CG, data); WREG32 1603 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CG, data); WREG32 1607 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_HUB_CG, data); WREG32 1611 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_SIP_CG, data); WREG32 1615 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_HUB_MISC_VM_CG, data); WREG32 1619 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_XPB_CLK_GAT, data); WREG32 1623 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmATC_MISC_CG, data); WREG32 1627 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_WR_CG, data); WREG32 1631 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_RD_CG, data); WREG32 1635 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmMC_CITF_MISC_VM_CG, data); WREG32 1639 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c WREG32(mmVM_L2_CG, data); WREG32 216 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); WREG32 222 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); WREG32 230 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); WREG32 236 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); WREG32 308 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); WREG32 319 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); WREG32 1395 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); WREG32 67 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_CNTL, ih_cntl); WREG32 68 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 86 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 87 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_CNTL, ih_cntl); WREG32 89 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_RPTR, 0); WREG32 90 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_WPTR, 0); WREG32 116 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); WREG32 124 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmINTERRUPT_CNTL, interrupt_cntl); WREG32 127 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); WREG32 138 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); WREG32 139 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); WREG32 141 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 144 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_RPTR, 0); WREG32 145 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_WPTR, 0); WREG32 153 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_CNTL, ih_cntl); WREG32 207 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_CNTL, tmp); WREG32 254 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_RB_RPTR, ih->rptr); WREG32 372 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 378 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 132 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32(mmDOUT_SCRATCH3, v); WREG32 449 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32(config_regs->offset, data); WREG32 37 drivers/gpu/drm/amd/amdgpu/kv_smc.c WREG32(mmSMC_MESSAGE_0, id & SMC_MESSAGE_0__SMC_MSG_MASK); WREG32 72 drivers/gpu/drm/amd/amdgpu/kv_smc.c WREG32(mmSMC_MSG_ARG_0, parameter); WREG32 85 drivers/gpu/drm/amd/amdgpu/kv_smc.c WREG32(mmSMC_IND_INDEX_0, smc_address); WREG32 168 drivers/gpu/drm/amd/amdgpu/kv_smc.c WREG32(mmSMC_IND_DATA_0, data); WREG32 181 drivers/gpu/drm/amd/amdgpu/kv_smc.c WREG32(mmSMC_IND_DATA_0, data); WREG32 214 drivers/gpu/drm/amd/amdgpu/kv_smc.c WREG32(mmSMC_IND_DATA_0, data); WREG32 91 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32(reg, doorbell_range); WREG32 111 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32(reg, doorbell_range); WREG32 84 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32(reg, doorbell_range); WREG32 91 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32(reg, doorbell_range); WREG32 111 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32(reg, doorbell_range); WREG32 122 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32(reg, doorbell_range); WREG32 148 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32(reg, doorbell_range); WREG32 70 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(address, reg); WREG32 85 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(address, reg); WREG32 87 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(data, v); WREG32 101 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(address, (reg)); WREG32 115 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(address, (reg)); WREG32 116 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(data, (v)); WREG32 140 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); WREG32 343 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); WREG32 677 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); WREG32 711 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); WREG32 497 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); WREG32 531 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); WREG32 575 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); WREG32 618 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); WREG32 226 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); WREG32 353 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32 356 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); WREG32 398 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); WREG32 426 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); WREG32 427 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); WREG32 432 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], WREG32 435 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); WREG32 446 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32 449 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); WREG32 450 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); WREG32 451 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); WREG32 452 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); WREG32 455 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], WREG32 457 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], WREG32 462 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); WREG32 463 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); WREG32 466 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); WREG32 470 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32 478 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); WREG32 973 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); WREG32 980 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); WREG32 988 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 994 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1017 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); WREG32 1022 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); WREG32 1033 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); WREG32 1038 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); WREG32 399 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); WREG32 527 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32 530 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); WREG32 593 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], WREG32 595 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], WREG32 605 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); WREG32 633 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); WREG32 664 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); WREG32 665 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); WREG32 670 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], WREG32 673 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); WREG32 684 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32 688 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); WREG32 690 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); WREG32 691 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); WREG32 694 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], WREG32 696 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], WREG32 701 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); WREG32 702 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); WREG32 713 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); WREG32 718 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], WREG32 720 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], WREG32 725 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); WREG32 734 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); WREG32 738 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32 746 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); WREG32 1322 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1328 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1351 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); WREG32 1356 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); WREG32 1367 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); WREG32 1372 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); WREG32 1458 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); WREG32 1473 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); WREG32 1491 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); WREG32 1499 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); WREG32 77 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) WREG32 1166 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); WREG32 1172 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); WREG32 1184 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); WREG32 1190 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); WREG32 1200 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); WREG32 349 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), WREG32 351 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), WREG32 512 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); WREG32 515 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); WREG32 576 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), WREG32 578 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), WREG32 580 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), WREG32 583 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); WREG32 609 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); WREG32 638 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); WREG32 649 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); WREG32 652 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); WREG32 653 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); WREG32 654 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); WREG32 655 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); WREG32 659 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), WREG32 661 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), WREG32 668 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), WREG32 672 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), WREG32 674 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), WREG32 679 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); WREG32 680 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); WREG32 685 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); WREG32 688 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); WREG32 689 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); WREG32 702 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); WREG32 703 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); WREG32 712 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); WREG32 720 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); WREG32 726 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); WREG32 733 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); WREG32 739 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); WREG32 744 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); WREG32 752 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); WREG32 817 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); WREG32 822 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); WREG32 825 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); WREG32 1384 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_gfx_preempt, 1); WREG32 1400 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_gfx_preempt, 0); WREG32 1421 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(reg_offset, sdma_cntl); WREG32 1494 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); WREG32 1507 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); WREG32 1524 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); WREG32 1531 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); WREG32 910 drivers/gpu/drm/amd/amdgpu/si.c WREG32(AMDGPU_PCIE_INDEX, reg); WREG32 922 drivers/gpu/drm/amd/amdgpu/si.c WREG32(AMDGPU_PCIE_INDEX, reg); WREG32 924 drivers/gpu/drm/amd/amdgpu/si.c WREG32(AMDGPU_PCIE_DATA, v); WREG32 935 drivers/gpu/drm/amd/amdgpu/si.c WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); WREG32 947 drivers/gpu/drm/amd/amdgpu/si.c WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); WREG32 949 drivers/gpu/drm/amd/amdgpu/si.c WREG32(PCIE_PORT_DATA, (v)); WREG32 960 drivers/gpu/drm/amd/amdgpu/si.c WREG32(SMC_IND_INDEX_0, (reg)); WREG32 971 drivers/gpu/drm/amd/amdgpu/si.c WREG32(SMC_IND_INDEX_0, (reg)); WREG32 972 drivers/gpu/drm/amd/amdgpu/si.c WREG32(SMC_IND_DATA_0, (v)); WREG32 1129 drivers/gpu/drm/amd/amdgpu/si.c WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); WREG32 1132 drivers/gpu/drm/amd/amdgpu/si.c WREG32(AVIVO_D1VGA_CONTROL, WREG32 1135 drivers/gpu/drm/amd/amdgpu/si.c WREG32(AVIVO_D2VGA_CONTROL, WREG32 1138 drivers/gpu/drm/amd/amdgpu/si.c WREG32(VGA_RENDER_CONTROL, WREG32 1141 drivers/gpu/drm/amd/amdgpu/si.c WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); WREG32 1146 drivers/gpu/drm/amd/amdgpu/si.c WREG32(R600_BUS_CNTL, bus_cntl); WREG32 1148 drivers/gpu/drm/amd/amdgpu/si.c WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); WREG32 1149 drivers/gpu/drm/amd/amdgpu/si.c WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); WREG32 1150 drivers/gpu/drm/amd/amdgpu/si.c WREG32(VGA_RENDER_CONTROL, vga_render_control); WREG32 1152 drivers/gpu/drm/amd/amdgpu/si.c WREG32(R600_ROM_CNTL, rom_cntl); WREG32 1176 drivers/gpu/drm/amd/amdgpu/si.c WREG32(mmROM_INDEX, 0); WREG32 1211 drivers/gpu/drm/amd/amdgpu/si.c WREG32(CONFIG_CNTL, temp); WREG32 1245 drivers/gpu/drm/amd/amdgpu/si.c WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); WREG32 1256 drivers/gpu/drm/amd/amdgpu/si.c WREG32(mmHDP_DEBUG0, 1); WREG32 1788 drivers/gpu/drm/amd/amdgpu/si.c WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); WREG32 1799 drivers/gpu/drm/amd/amdgpu/si.c WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); WREG32 1800 drivers/gpu/drm/amd/amdgpu/si.c WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); WREG32 1810 drivers/gpu/drm/amd/amdgpu/si.c WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); WREG32 1821 drivers/gpu/drm/amd/amdgpu/si.c WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); WREG32 1822 drivers/gpu/drm/amd/amdgpu/si.c WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); WREG32 1975 drivers/gpu/drm/amd/amdgpu/si.c WREG32(THM_CLK_CNTL, data); WREG32 1981 drivers/gpu/drm/amd/amdgpu/si.c WREG32(MISC_CLK_CNTL, data); WREG32 1986 drivers/gpu/drm/amd/amdgpu/si.c WREG32(CG_CLKPIN_CNTL, data); WREG32 1991 drivers/gpu/drm/amd/amdgpu/si.c WREG32(CG_CLKPIN_CNTL_2, data); WREG32 1997 drivers/gpu/drm/amd/amdgpu/si.c WREG32(MPLL_BYPASSCLK_SEL, data); WREG32 2002 drivers/gpu/drm/amd/amdgpu/si.c WREG32(SPLL_CNTL_MODE, data); WREG32 59 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_WPTR + sdma_offsets[me], WREG32 123 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32 141 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); WREG32 142 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); WREG32 150 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32 153 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); WREG32 154 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_WPTR + sdma_offsets[i], 0); WREG32 158 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); WREG32 159 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); WREG32 163 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); WREG32 170 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); WREG32 174 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); WREG32 177 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); WREG32 178 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); WREG32 599 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); WREG32 604 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); WREG32 615 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); WREG32 620 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); WREG32 662 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_POWER_CNTL + offset, data); WREG32 663 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_CLK_CTRL + offset, 0x00000100); WREG32 674 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_POWER_CNTL + offset, data); WREG32 679 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_CLK_CTRL + offset, data); WREG32 693 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_PGFSM_WRITE, 0x00002000); WREG32 694 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_PGFSM_CONFIG, 0x100010ff); WREG32 697 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_PGFSM_WRITE, 0); WREG32 2771 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_CAC_CTRL, reg); WREG32 2868 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(config_regs->offset, data); WREG32 3116 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); WREG32 3117 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); WREG32 3121 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); WREG32 3122 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); WREG32 3126 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); WREG32 3127 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); WREG32 3131 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); WREG32 3132 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); WREG32 3140 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_CG_CONFIG, mc_cg_config); WREG32 3675 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); WREG32 3847 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(SMC_SCRATCH0, parameter); WREG32 4066 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); WREG32 4077 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); WREG32 4163 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32 4182 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); WREG32 4226 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_BSP, pi->dsp); WREG32 4240 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); WREG32 4256 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_TPC, R600_TPC_DFLT); WREG32 4261 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); WREG32 4275 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32 4282 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FTV, pi->vrc); WREG32 4287 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FTV, 0); WREG32 5230 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); WREG32 5231 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); WREG32 5999 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); WREG32 6000 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); WREG32 6001 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); WREG32 6002 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); WREG32 6003 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); WREG32 6004 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); WREG32 6005 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); WREG32 6006 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); WREG32 6007 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); WREG32 6008 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); WREG32 6009 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); WREG32 6010 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); WREG32 6011 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); WREG32 6012 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); WREG32 6404 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_THERMAL_INT, thermal_int); WREG32 6412 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_THERMAL_INT, thermal_int); WREG32 6458 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); WREG32 6462 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); WREG32 6618 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL0, tmp); WREG32 6698 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_TACH_CTRL, tmp); WREG32 6714 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); WREG32 6718 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); WREG32 6738 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_TACH_CTRL, tmp); WREG32 6743 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); WREG32 40 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_CNTL, ih_cntl); WREG32 41 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 52 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 53 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_CNTL, ih_cntl); WREG32 54 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_RPTR, 0); WREG32 55 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_WPTR, 0); WREG32 68 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); WREG32 72 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(INTERRUPT_CNTL, interrupt_cntl); WREG32 74 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); WREG32 82 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); WREG32 83 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); WREG32 84 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 85 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_RPTR, 0); WREG32 86 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_WPTR, 0); WREG32 91 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_CNTL, ih_cntl); WREG32 119 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_CNTL, tmp); WREG32 148 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_RB_RPTR, ih->rptr); WREG32 250 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 256 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 41 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32(SMC_IND_INDEX_0, smc_address); WREG32 71 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 102 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 173 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32(SMC_MESSAGE_0, msg); WREG32 228 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32(SMC_IND_INDEX_0, ucode_start_address); WREG32 234 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 269 drivers/gpu/drm/amd/amdgpu/si_smc.c WREG32(SMC_IND_DATA_0, value); WREG32 105 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg); WREG32 120 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg); WREG32 122 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(data, v); WREG32 136 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg); WREG32 141 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg + 4); WREG32 157 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg); WREG32 159 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(data, (u32)(v & 0xffffffffULL)); WREG32 163 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg + 4); WREG32 165 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(data, (u32)(v >> 32)); WREG32 179 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, ((reg) & 0x1ff)); WREG32 193 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, ((reg) & 0x1ff)); WREG32 194 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(data, (v)); WREG32 207 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, (reg)); WREG32 221 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, (reg)); WREG32 222 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(data, (v)); WREG32 341 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(rom_index_offset, 0); WREG32 462 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(reg, tmp); WREG32 1365 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); WREG32 1375 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); WREG32 1405 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); WREG32 1420 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); WREG32 1438 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); WREG32 31 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ WREG32 42 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) WREG32 48 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value) WREG32 82 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(r0, value); \ WREG32 83 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(r1, (reg | 0x80000000)); \ WREG32 84 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(spare_int, 0x1); \ WREG32 94 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(reg, value); \ WREG32 107 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(r2, value); \ WREG32 109 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(r3, value); \ WREG32 110 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(target_reg, value); \ WREG32 112 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(target_reg, value); \ WREG32 66 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 83 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 85 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_RPTR, 0); WREG32 86 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_WPTR, 0); WREG32 112 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); WREG32 120 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmINTERRUPT_CNTL, interrupt_cntl); WREG32 123 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8); WREG32 135 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_CNTL, ih_rb_cntl); WREG32 138 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); WREG32 139 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); WREG32 142 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_RPTR, 0); WREG32 143 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_WPTR, 0); WREG32 155 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); WREG32 209 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_CNTL, tmp); WREG32 261 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmIH_RB_RPTR, ih->rptr); WREG32 423 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 429 drivers/gpu/drm/amd/amdgpu/tonga_ih.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 98 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); WREG32 104 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); WREG32 109 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); WREG32 115 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); WREG32 231 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); WREG32 233 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); WREG32 238 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); WREG32 239 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); WREG32 90 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 268 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_CGC_GATE, 0); WREG32 275 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_VCPU_CNTL, 1 << 9); WREG32 285 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); WREG32 286 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); WREG32 288 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_LMI_CTRL, 0x203108); WREG32 291 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_MPC_CNTL, tmp | 0x10); WREG32 293 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); WREG32 294 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_MPC_SET_MUXA1, 0x0); WREG32 295 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); WREG32 296 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_MPC_SET_MUXB1, 0x0); WREG32 297 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_MPC_SET_ALU, 0); WREG32 298 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_MPC_SET_MUX, 0x88); WREG32 348 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); WREG32 351 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); WREG32 354 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | WREG32 358 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_RBC_RB_RPTR, 0x0); WREG32 361 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 364 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); WREG32 386 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); WREG32 429 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | WREG32 433 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_STATUS, 0); WREG32 482 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); WREG32 549 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); WREG32 550 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_VCPU_CACHE_SIZE0, size); WREG32 554 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); WREG32 555 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_VCPU_CACHE_SIZE1, size); WREG32 560 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); WREG32 561 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_VCPU_CACHE_SIZE2, size); WREG32 565 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); WREG32 569 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); WREG32 571 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 572 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 573 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 589 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_CGC_CTRL, data); WREG32 598 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_CGC_CTRL, data); WREG32 625 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_CGC_CTRL, tmp); WREG32 702 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | WREG32 713 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | WREG32 88 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 259 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, WREG32 261 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, WREG32 266 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); WREG32 267 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_VCPU_CACHE_SIZE0, size); WREG32 271 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); WREG32 272 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_VCPU_CACHE_SIZE1, size); WREG32 277 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); WREG32 278 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_VCPU_CACHE_SIZE2, size); WREG32 280 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 281 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 282 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 317 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | WREG32 329 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | WREG32 337 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); WREG32 338 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); WREG32 340 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); WREG32 341 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_MPC_SET_MUXA1, 0x0); WREG32 342 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); WREG32 343 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_MPC_SET_MUXB1, 0x0); WREG32 344 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_MPC_SET_ALU, 0); WREG32 345 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_MPC_SET_MUX, 0x88); WREG32 348 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); WREG32 352 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_VCPU_CNTL, 1 << 9); WREG32 358 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_SOFT_RESET, 0); WREG32 401 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_RBC_RB_CNTL, tmp); WREG32 404 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); WREG32 407 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); WREG32 410 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, WREG32 412 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, WREG32 416 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_RBC_RB_RPTR, 0); WREG32 419 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 436 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); WREG32 443 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); WREG32 447 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_VCPU_CNTL, 0x0); WREG32 452 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_STATUS, 0); WREG32 499 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); WREG32 644 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_SUVD_CGC_GATE, data1); WREG32 645 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_CGC_GATE, data3); WREG32 691 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_CGC_CTRL, data); WREG32 692 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_SUVD_CGC_CTRL, data2); WREG32 731 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_CGC_GATE, data); WREG32 732 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_SUVD_CGC_GATE, data1); WREG32 749 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_CGC_CTRL, data); WREG32 758 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_CGC_CTRL, data); WREG32 142 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 157 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_WPTR, WREG32 160 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_WPTR2, WREG32 585 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, WREG32 587 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, WREG32 592 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); WREG32 593 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_VCPU_CACHE_SIZE0, size); WREG32 597 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); WREG32 598 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_VCPU_CACHE_SIZE1, size); WREG32 603 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); WREG32 604 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_VCPU_CACHE_SIZE2, size); WREG32 606 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 607 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 608 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32 610 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); WREG32 687 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_CGC_GATE, data); WREG32 688 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_SUVD_CGC_GATE, data1); WREG32 724 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_SOFT_RESET, WREG32 740 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_LMI_CTRL, WREG32 753 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); WREG32 754 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); WREG32 756 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); WREG32 757 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_MPC_SET_MUXA1, 0x0); WREG32 758 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); WREG32 759 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_MPC_SET_MUXB1, 0x0); WREG32 760 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_MPC_SET_ALU, 0); WREG32 761 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_MPC_SET_MUX, 0x88); WREG32 764 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); WREG32 768 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); WREG32 774 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_SOFT_RESET, 0); WREG32 818 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RBC_RB_CNTL, tmp); WREG32 821 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); WREG32 824 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); WREG32 827 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, WREG32 829 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, WREG32 833 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RBC_RB_RPTR, 0); WREG32 836 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 842 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); WREG32 843 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 844 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr); WREG32 845 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); WREG32 846 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_SIZE, ring->ring_size / 4); WREG32 849 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); WREG32 850 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); WREG32 851 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr); WREG32 852 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); WREG32 853 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4); WREG32 869 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); WREG32 876 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); WREG32 880 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_VCPU_CNTL, 0x0); WREG32 885 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_STATUS, 0); WREG32 962 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); WREG32 1179 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1185 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1299 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_SUVD_CGC_GATE, data1); WREG32 1300 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_CGC_GATE, data3); WREG32 1347 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_CGC_CTRL, data); WREG32 1348 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_SUVD_CGC_CTRL, data2); WREG32 1389 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_CGC_GATE, data); WREG32 1390 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_SUVD_CGC_GATE, data1); WREG32 1407 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_CGC_CTRL, data); WREG32 1416 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_CGC_CTRL, data); WREG32 1454 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); WREG32 1502 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 1508 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 94 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 96 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); WREG32 144 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7); WREG32 155 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_CLOCK_GATING_A, tmp); WREG32 160 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_UENC_CLOCK_GATING, tmp); WREG32 165 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_CLOCK_GATING_B, tmp); WREG32 175 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_CLOCK_GATING_B, 0xf7); WREG32 177 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_LMI_CTRL, 0x00398000); WREG32 179 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_LMI_SWAP_CNTL, 0); WREG32 180 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_LMI_SWAP_CNTL1, 0); WREG32 181 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_LMI_VM_CTRL, 0); WREG32 183 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); WREG32 187 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); WREG32 188 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_VCPU_CACHE_SIZE0, size); WREG32 192 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); WREG32 193 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_VCPU_CACHE_SIZE1, size); WREG32 197 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); WREG32 198 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_VCPU_CACHE_SIZE2, size); WREG32 244 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); WREG32 245 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 246 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); WREG32 247 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); WREG32 248 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); WREG32 251 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); WREG32 252 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); WREG32 253 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); WREG32 254 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); WREG32 255 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); WREG32 305 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_STATUS, 0); WREG32 317 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_CLOCK_GATING_B, tmp); WREG32 321 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_UENC_CLOCK_GATING, tmp); WREG32 325 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); WREG32 327 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0); WREG32 332 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_CLOCK_GATING_B, tmp); WREG32 337 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_UENC_CLOCK_GATING, tmp); WREG32 341 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); WREG32 358 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_CLOCK_GATING_B, tmp); WREG32 362 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_CLOCK_GATING_B, tmp); WREG32 369 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_UENC_CLOCK_GATING, tmp); WREG32 374 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); WREG32 377 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00); WREG32 380 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0); WREG32 85 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); WREG32 87 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); WREG32 96 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); WREG32 117 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); WREG32 119 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); WREG32 128 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); WREG32 148 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); WREG32 150 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); WREG32 153 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 155 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); WREG32 157 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); WREG32 159 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); WREG32 185 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_CLOCK_GATING_B, data); WREG32 190 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_UENC_CLOCK_GATING, data); WREG32 195 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_UENC_CLOCK_GATING_2, data); WREG32 199 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_UENC_REG_CLOCK_GATING, data); WREG32 206 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data); WREG32 211 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_CLOCK_GATING_B, data); WREG32 215 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_UENC_CLOCK_GATING, data); WREG32 219 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_UENC_CLOCK_GATING_2, data); WREG32 223 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_UENC_REG_CLOCK_GATING, data); WREG32 230 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data); WREG32 275 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx)); WREG32 281 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); WREG32 282 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); WREG32 283 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); WREG32 284 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); WREG32 285 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); WREG32 288 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); WREG32 289 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); WREG32 290 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); WREG32 291 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); WREG32 292 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); WREG32 295 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); WREG32 296 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); WREG32 297 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); WREG32 298 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); WREG32 299 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4); WREG32 325 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); WREG32 340 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx)); WREG32 351 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_STATUS, 0); WREG32 354 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); WREG32 531 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_CLOCK_GATING_B, 0x1FF); WREG32 533 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_LMI_CTRL, 0x00398000); WREG32 535 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_LMI_SWAP_CNTL, 0); WREG32 536 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_LMI_SWAP_CNTL1, 0); WREG32 537 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_LMI_VM_CTRL, 0); WREG32 541 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); WREG32 542 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); WREG32 543 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8)); WREG32 545 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); WREG32 548 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); WREG32 549 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_VCPU_CACHE_SIZE0, size); WREG32 554 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); WREG32 555 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_VCPU_CACHE_SIZE1, size); WREG32 558 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); WREG32 559 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_VCPU_CACHE_SIZE2, size); WREG32 563 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff); WREG32 564 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_VCPU_CACHE_SIZE1, size); WREG32 567 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff); WREG32 568 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_VCPU_CACHE_SIZE2, size); WREG32 623 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); WREG32 628 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); WREG32 633 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); WREG32 660 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 666 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 754 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i)); WREG32 761 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_CLOCK_GATING_A, data); WREG32 767 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_UENC_CLOCK_GATING, data); WREG32 773 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); WREG32 114 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), WREG32 117 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), WREG32 120 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), WREG32 163 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr)); WREG32 164 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr)); WREG32 170 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data); WREG32 173 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size); WREG32 176 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0); WREG32 184 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001); WREG32 342 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); WREG32 343 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); WREG32 344 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr); WREG32 345 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); WREG32 346 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), ring->ring_size / 4); WREG32 350 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr)); WREG32 351 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr)); WREG32 352 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO2), ring->gpu_addr); WREG32 353 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr)); WREG32 354 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE2), ring->ring_size / 4); WREG32 358 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr)); WREG32 359 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr)); WREG32 360 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO3), ring->gpu_addr); WREG32 361 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr)); WREG32 362 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE3), ring->ring_size / 4); WREG32 399 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0); WREG32 610 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), 0x1FF); WREG32 612 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x00398000); WREG32 614 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0); WREG32 615 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0); WREG32 616 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); WREG32 623 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), WREG32 625 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), WREG32 627 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0); WREG32 629 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), WREG32 631 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), WREG32 633 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & ~0x0f000000); WREG32 637 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); WREG32 639 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8)); WREG32 640 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xff); WREG32 643 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), (offset & ~0x0f000000) | (1 << 24)); WREG32 644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size); WREG32 646 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8)); WREG32 647 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xff); WREG32 650 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), (offset & ~0x0f000000) | (2 << 24)); WREG32 651 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size); WREG32 752 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 758 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(mmSRBM_SOFT_RESET, tmp); WREG32 804 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL), data); WREG32 824 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data); WREG32 829 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data); WREG32 834 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data); WREG32 838 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data); WREG32 845 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data); WREG32 850 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data); WREG32 854 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data); WREG32 858 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data); WREG32 862 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data); WREG32 869 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data); WREG32 914 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A, data); WREG32 920 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING, data); WREG32 674 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp); WREG32 687 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp); WREG32 765 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp); WREG32 768 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp); WREG32 2102 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); WREG32 142 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmMP0PUB_IND_INDEX, (reg)); WREG32 153 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmMP0PUB_IND_INDEX, (reg)); WREG32 154 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmMP0PUB_IND_DATA, (v)); WREG32 164 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32 175 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32 176 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmUVD_CTX_DATA, (v)); WREG32 186 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmDIDT_IND_INDEX, (reg)); WREG32 197 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmDIDT_IND_INDEX, (reg)); WREG32 198 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmDIDT_IND_DATA, (v)); WREG32 208 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmGC_CAC_IND_INDEX, (reg)); WREG32 219 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmGC_CAC_IND_INDEX, (reg)); WREG32 220 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmGC_CAC_IND_DATA, (v)); WREG32 367 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); WREG32 393 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); WREG32 396 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmD1VGA_CONTROL, WREG32 399 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmD2VGA_CONTROL, WREG32 402 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmVGA_RENDER_CONTROL, WREG32 410 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmBUS_CNTL, bus_cntl); WREG32 412 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmD1VGA_CONTROL, d1vga_control); WREG32 413 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmD2VGA_CONTROL, d2vga_control); WREG32 414 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmVGA_RENDER_CONTROL, vga_render_control); WREG32 440 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX); WREG32 441 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmSMC_IND_DATA_11, 0); WREG32 443 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmSMC_IND_INDEX_11, ixROM_DATA); WREG32 892 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmBIF_DOORBELL_APER_EN, tmp); WREG32 912 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); WREG32 923 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmHDP_DEBUG0, 1); WREG32 1390 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmHDP_HOST_PATH_CNTL, data); WREG32 1406 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmHDP_MEM_POWER_LS, data); WREG32 1422 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(0x157a, data); WREG32 53 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c WREG32(reg, value << shift); WREG32 58 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c WREG32(reg, data); WREG32 40 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c WREG32(0x12074, 0xFFF0003B); WREG32 1152 drivers/gpu/drm/mgag200/mgag200_mode.c WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000); WREG32 1154 drivers/gpu/drm/mgag200/mgag200_mode.c WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000); WREG32 239 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); WREG32 248 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); WREG32 405 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); WREG32 410 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); WREG32 421 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); WREG32 426 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); WREG32 1370 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1VGA_CONTROL, 0); WREG32 1373 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D2VGA_CONTROL, 0); WREG32 1376 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_D3VGA_CONTROL, 0); WREG32 1379 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_D4VGA_CONTROL, 0); WREG32 1382 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_D5VGA_CONTROL, 0); WREG32 1385 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_D6VGA_CONTROL, 0); WREG32 1394 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); WREG32 1396 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, WREG32 1398 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, WREG32 1400 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, WREG32 1402 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, WREG32 1404 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); WREG32 1405 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); WREG32 1419 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); WREG32 1420 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); WREG32 1421 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); WREG32 1422 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); WREG32 1423 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); WREG32 1424 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); WREG32 1427 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); WREG32 1428 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); WREG32 1431 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, WREG32 1434 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, WREG32 1438 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, WREG32 1445 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, WREG32 1449 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); WREG32 1602 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1VGA_CONTROL, 0); WREG32 1604 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D2VGA_CONTROL, 0); WREG32 1609 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); WREG32 1613 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); WREG32 1614 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); WREG32 1616 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); WREG32 1617 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); WREG32 1620 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, WREG32 1622 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + WREG32 1624 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); WREG32 1626 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); WREG32 1635 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); WREG32 1636 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); WREG32 1637 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); WREG32 1638 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); WREG32 1639 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); WREG32 1640 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); WREG32 1643 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); WREG32 1644 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); WREG32 1646 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, WREG32 1650 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, WREG32 1654 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, WREG32 1658 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); WREG32 1716 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); WREG32 1721 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); WREG32 1722 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); WREG32 1723 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); WREG32 2181 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); WREG32 2183 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); WREG32 75 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); WREG32 77 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); WREG32 1561 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(reg, (ATOM_S3_TV1_ACTIVE | WREG32 1564 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); WREG32 1566 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(reg, 0); WREG32 1574 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(reg, temp); WREG32 1635 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); WREG32 1637 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(RADEON_BIOS_3_SCRATCH, reg); WREG32 2078 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); WREG32 2087 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, WREG32 2090 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); WREG32 2093 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, WREG32 2096 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); WREG32 2099 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, WREG32 2102 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); WREG32 1347 drivers/gpu/drm/radeon/btc_dpm.c WREG32(CG_BIF_REQ_AND_RSP, bif); WREG32 1366 drivers/gpu/drm/radeon/btc_dpm.c WREG32(CG_BIF_REQ_AND_RSP, bif); WREG32 1419 drivers/gpu/drm/radeon/btc_dpm.c WREG32(CG_ULV_CONTROL, BTC_CGULVCONTROL_DFLT); WREG32 1420 drivers/gpu/drm/radeon/btc_dpm.c WREG32(CG_ULV_PARAMETER, BTC_CGULVPARAMETER_DFLT); WREG32 1451 drivers/gpu/drm/radeon/btc_dpm.c WREG32(sequence[i], tmp); WREG32 1772 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_ARB_DRAM_TIMING, arb_registers->mc_arb_dram_timing); WREG32 1773 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_ARB_DRAM_TIMING2, arb_registers->mc_arb_dram_timing2); WREG32 2031 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); WREG32 2032 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); WREG32 2033 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); WREG32 2034 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); WREG32 2035 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); WREG32 2036 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); WREG32 2037 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); WREG32 2038 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); WREG32 2039 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); WREG32 2040 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); WREG32 2041 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); WREG32 2077 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_PMG_AUTO_CFG, tmp); WREG32 606 drivers/gpu/drm/radeon/ci_dpm.c WREG32(config_regs->offset << 2, data); WREG32 1665 drivers/gpu/drm/radeon/ci_dpm.c WREG32(SMC_MESSAGE_0, msg); WREG32 1681 drivers/gpu/drm/radeon/ci_dpm.c WREG32(SMC_MSG_ARG_0, parameter); WREG32 1929 drivers/gpu/drm/radeon/ci_dpm.c WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); WREG32 1940 drivers/gpu/drm/radeon/ci_dpm.c WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); WREG32 4614 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_IO_DEBUG_INDEX, 3); WREG32 4617 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_IO_DEBUG_INDEX, 3); WREG32 4618 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_IO_DEBUG_DATA, tmp); WREG32 4636 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); WREG32 4637 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); WREG32 4638 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY)); WREG32 4639 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0)); WREG32 4640 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1)); WREG32 4641 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL)); WREG32 4642 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD)); WREG32 4643 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL)); WREG32 4644 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); WREG32 4645 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); WREG32 4646 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); WREG32 4647 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); WREG32 4648 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); WREG32 4649 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); WREG32 4650 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); WREG32 4651 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); WREG32 4652 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); WREG32 4653 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); WREG32 4654 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); WREG32 4655 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); WREG32 41 drivers/gpu/drm/radeon/ci_smc.c WREG32(SMC_IND_INDEX_0, smc_address); WREG32 73 drivers/gpu/drm/radeon/ci_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 105 drivers/gpu/drm/radeon/ci_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 229 drivers/gpu/drm/radeon/ci_smc.c WREG32(SMC_IND_INDEX_0, ucode_start_address); WREG32 235 drivers/gpu/drm/radeon/ci_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 270 drivers/gpu/drm/radeon/ci_smc.c WREG32(SMC_IND_DATA_0, value); WREG32 194 drivers/gpu/drm/radeon/cik.c WREG32(CIK_DIDT_IND_INDEX, (reg)); WREG32 205 drivers/gpu/drm/radeon/cik.c WREG32(CIK_DIDT_IND_INDEX, (reg)); WREG32 206 drivers/gpu/drm/radeon/cik.c WREG32(CIK_DIDT_IND_DATA, (v)); WREG32 256 drivers/gpu/drm/radeon/cik.c WREG32(PCIE_INDEX, reg); WREG32 268 drivers/gpu/drm/radeon/cik.c WREG32(PCIE_INDEX, reg); WREG32 270 drivers/gpu/drm/radeon/cik.c WREG32(PCIE_DATA, v); WREG32 1861 drivers/gpu/drm/radeon/cik.c WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); WREG32 1919 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_SUP_CNTL, 0x00000008); WREG32 1920 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_SUP_CNTL, 0x00000010); WREG32 1925 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); WREG32 1926 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); WREG32 1928 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); WREG32 1929 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); WREG32 1935 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_IO_DEBUG_INDEX, 5); WREG32 1936 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023); WREG32 1937 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_IO_DEBUG_INDEX, 9); WREG32 1938 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0); WREG32 1944 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); WREG32 1946 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); WREG32 1950 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_SUP_CNTL, 0x00000008); WREG32 1951 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_SUP_CNTL, 0x00000004); WREG32 1952 drivers/gpu/drm/radeon/cik.c WREG32(MC_SEQ_SUP_CNTL, 0x00000001); WREG32 2507 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); WREG32 2509 drivers/gpu/drm/radeon/cik.c WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); WREG32 2650 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); WREG32 2652 drivers/gpu/drm/radeon/cik.c WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); WREG32 2875 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); WREG32 2877 drivers/gpu/drm/radeon/cik.c WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); WREG32 3018 drivers/gpu/drm/radeon/cik.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); WREG32 3020 drivers/gpu/drm/radeon/cik.c WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); WREG32 3052 drivers/gpu/drm/radeon/cik.c WREG32(GRBM_GFX_INDEX, data); WREG32 3169 drivers/gpu/drm/radeon/cik.c WREG32(PA_SC_RASTER_CONFIG, data); WREG32 3265 drivers/gpu/drm/radeon/cik.c WREG32((0x2c14 + j), 0x00000000); WREG32 3266 drivers/gpu/drm/radeon/cik.c WREG32((0x2c18 + j), 0x00000000); WREG32 3267 drivers/gpu/drm/radeon/cik.c WREG32((0x2c1c + j), 0x00000000); WREG32 3268 drivers/gpu/drm/radeon/cik.c WREG32((0x2c20 + j), 0x00000000); WREG32 3269 drivers/gpu/drm/radeon/cik.c WREG32((0x2c24 + j), 0x00000000); WREG32 3272 drivers/gpu/drm/radeon/cik.c WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); WREG32 3273 drivers/gpu/drm/radeon/cik.c WREG32(SRBM_INT_CNTL, 0x1); WREG32 3274 drivers/gpu/drm/radeon/cik.c WREG32(SRBM_INT_ACK, 0x1); WREG32 3276 drivers/gpu/drm/radeon/cik.c WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); WREG32 3338 drivers/gpu/drm/radeon/cik.c WREG32(GB_ADDR_CONFIG, gb_addr_config); WREG32 3339 drivers/gpu/drm/radeon/cik.c WREG32(HDP_ADDR_CONFIG, gb_addr_config); WREG32 3340 drivers/gpu/drm/radeon/cik.c WREG32(DMIF_ADDR_CALC, gb_addr_config); WREG32 3341 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); WREG32 3342 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); WREG32 3343 drivers/gpu/drm/radeon/cik.c WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); WREG32 3344 drivers/gpu/drm/radeon/cik.c WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); WREG32 3345 drivers/gpu/drm/radeon/cik.c WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); WREG32 3362 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); WREG32 3364 drivers/gpu/drm/radeon/cik.c WREG32(SX_DEBUG_1, 0x20); WREG32 3366 drivers/gpu/drm/radeon/cik.c WREG32(TA_CNTL_AUX, 0x00010000); WREG32 3370 drivers/gpu/drm/radeon/cik.c WREG32(SPI_CONFIG_CNTL, tmp); WREG32 3372 drivers/gpu/drm/radeon/cik.c WREG32(SQ_CONFIG, 1); WREG32 3374 drivers/gpu/drm/radeon/cik.c WREG32(DB_DEBUG, 0); WREG32 3378 drivers/gpu/drm/radeon/cik.c WREG32(DB_DEBUG2, tmp); WREG32 3382 drivers/gpu/drm/radeon/cik.c WREG32(DB_DEBUG3, tmp); WREG32 3386 drivers/gpu/drm/radeon/cik.c WREG32(CB_HW_CONTROL, tmp); WREG32 3388 drivers/gpu/drm/radeon/cik.c WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); WREG32 3390 drivers/gpu/drm/radeon/cik.c WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) | WREG32 3395 drivers/gpu/drm/radeon/cik.c WREG32(VGT_NUM_INSTANCES, 1); WREG32 3397 drivers/gpu/drm/radeon/cik.c WREG32(CP_PERFMON_CNTL, 0); WREG32 3399 drivers/gpu/drm/radeon/cik.c WREG32(SQ_CONFIG, 0); WREG32 3401 drivers/gpu/drm/radeon/cik.c WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | WREG32 3404 drivers/gpu/drm/radeon/cik.c WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | WREG32 3407 drivers/gpu/drm/radeon/cik.c WREG32(VGT_GS_VERTEX_REUSE, 16); WREG32 3408 drivers/gpu/drm/radeon/cik.c WREG32(PA_SC_LINE_STIPPLE_STATE, 0); WREG32 3412 drivers/gpu/drm/radeon/cik.c WREG32(HDP_MISC_CNTL, tmp); WREG32 3415 drivers/gpu/drm/radeon/cik.c WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); WREG32 3417 drivers/gpu/drm/radeon/cik.c WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); WREG32 3418 drivers/gpu/drm/radeon/cik.c WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER); WREG32 3471 drivers/gpu/drm/radeon/cik.c WREG32(scratch, 0xCAFEDEAD); WREG32 3796 drivers/gpu/drm/radeon/cik.c WREG32(scratch, 0xCAFEDEAD); WREG32 3880 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_CNTL, 0); WREG32 3884 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); WREG32 3925 drivers/gpu/drm/radeon/cik.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 3927 drivers/gpu/drm/radeon/cik.c WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 3928 drivers/gpu/drm/radeon/cik.c WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version)); WREG32 3934 drivers/gpu/drm/radeon/cik.c WREG32(CP_CE_UCODE_ADDR, 0); WREG32 3936 drivers/gpu/drm/radeon/cik.c WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 3937 drivers/gpu/drm/radeon/cik.c WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version)); WREG32 3943 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 3945 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); WREG32 3946 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version)); WREG32 3947 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version)); WREG32 3953 drivers/gpu/drm/radeon/cik.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 3955 drivers/gpu/drm/radeon/cik.c WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 3956 drivers/gpu/drm/radeon/cik.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 3960 drivers/gpu/drm/radeon/cik.c WREG32(CP_CE_UCODE_ADDR, 0); WREG32 3962 drivers/gpu/drm/radeon/cik.c WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 3963 drivers/gpu/drm/radeon/cik.c WREG32(CP_CE_UCODE_ADDR, 0); WREG32 3967 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 3969 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); WREG32 3970 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 3991 drivers/gpu/drm/radeon/cik.c WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1); WREG32 3992 drivers/gpu/drm/radeon/cik.c WREG32(CP_ENDIAN_SWAP, 0); WREG32 3993 drivers/gpu/drm/radeon/cik.c WREG32(CP_DEVICE_ID, 1); WREG32 4068 drivers/gpu/drm/radeon/cik.c WREG32(CP_SEM_WAIT_TIMER, 0x0); WREG32 4070 drivers/gpu/drm/radeon/cik.c WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); WREG32 4073 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB_WPTR_DELAY, 0); WREG32 4076 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB_VMID, 0); WREG32 4078 drivers/gpu/drm/radeon/cik.c WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); WREG32 4088 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_CNTL, tmp); WREG32 4091 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); WREG32 4093 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_WPTR, ring->wptr); WREG32 4096 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); WREG32 4097 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); WREG32 4100 drivers/gpu/drm/radeon/cik.c WREG32(SCRATCH_UMSK, 0); WREG32 4106 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_CNTL, tmp); WREG32 4109 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_BASE, rb_addr); WREG32 4110 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr)); WREG32 4149 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_WPTR, ring->wptr); WREG32 4207 drivers/gpu/drm/radeon/cik.c WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); WREG32 4210 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_DEQUEUE_REQUEST, 1); WREG32 4216 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_DEQUEUE_REQUEST, 0); WREG32 4217 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_RPTR, 0); WREG32 4218 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_WPTR, 0); WREG32 4234 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_CNTL, 0); WREG32 4245 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); WREG32 4281 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME1_UCODE_ADDR, 0); WREG32 4283 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 4284 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version)); WREG32 4295 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME2_UCODE_ADDR, 0); WREG32 4297 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 4298 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version)); WREG32 4305 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME1_UCODE_ADDR, 0); WREG32 4307 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 4308 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME1_UCODE_ADDR, 0); WREG32 4313 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME2_UCODE_ADDR, 0); WREG32 4315 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 4316 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_ME2_UCODE_ADDR, 0); WREG32 4541 drivers/gpu/drm/radeon/cik.c WREG32(CP_CPF_DEBUG, tmp); WREG32 4554 drivers/gpu/drm/radeon/cik.c WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); WREG32 4555 drivers/gpu/drm/radeon/cik.c WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); WREG32 4558 drivers/gpu/drm/radeon/cik.c WREG32(CP_HPD_EOP_VMID, 0); WREG32 4564 drivers/gpu/drm/radeon/cik.c WREG32(CP_HPD_EOP_CONTROL, tmp); WREG32 4626 drivers/gpu/drm/radeon/cik.c WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); WREG32 4635 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_DOORBELL_CONTROL, WREG32 4643 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_DEQUEUE_REQUEST, 1); WREG32 4649 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); WREG32 4650 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); WREG32 4651 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); WREG32 4657 drivers/gpu/drm/radeon/cik.c WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); WREG32 4658 drivers/gpu/drm/radeon/cik.c WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); WREG32 4662 drivers/gpu/drm/radeon/cik.c WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); WREG32 4668 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); WREG32 4669 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); WREG32 4687 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); WREG32 4696 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); WREG32 4697 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI, WREG32 4708 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR, WREG32 4710 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI, WREG32 4727 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_DOORBELL_CONTROL, WREG32 4733 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); WREG32 4738 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); WREG32 4742 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); WREG32 4961 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); WREG32 4964 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); WREG32 4970 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); WREG32 4976 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); WREG32 5026 drivers/gpu/drm/radeon/cik.c WREG32(GRBM_SOFT_RESET, tmp); WREG32 5032 drivers/gpu/drm/radeon/cik.c WREG32(GRBM_SOFT_RESET, tmp); WREG32 5040 drivers/gpu/drm/radeon/cik.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 5046 drivers/gpu/drm/radeon/cik.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 5072 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP); WREG32 5073 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE | WREG32 5082 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5083 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0x200010ff); WREG32 5086 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5088 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5089 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0x300010ff); WREG32 5092 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5094 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0x210000); WREG32 5095 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff); WREG32 5098 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5100 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0x21003); WREG32 5101 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff); WREG32 5104 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5106 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0x2b00); WREG32 5107 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff); WREG32 5110 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5112 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5113 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff); WREG32 5116 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5118 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0x420000); WREG32 5119 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0x100010ff); WREG32 5122 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5124 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0x120202); WREG32 5125 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0x500010ff); WREG32 5128 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5130 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0x3e3e36); WREG32 5131 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0x600010ff); WREG32 5134 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5136 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0x373f3e); WREG32 5137 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0x700010ff); WREG32 5140 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0); WREG32 5142 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_WRITE, 0x3e1332); WREG32 5143 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff); WREG32 5145 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_MISC3, save->gmcon_misc3); WREG32 5146 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_MISC, save->gmcon_misc); WREG32 5147 drivers/gpu/drm/radeon/cik.c WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute); WREG32 5165 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); WREG32 5168 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); WREG32 5173 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); WREG32 5177 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); WREG32 5293 drivers/gpu/drm/radeon/cik.c WREG32((0x2c14 + j), 0x00000000); WREG32 5294 drivers/gpu/drm/radeon/cik.c WREG32((0x2c18 + j), 0x00000000); WREG32 5295 drivers/gpu/drm/radeon/cik.c WREG32((0x2c1c + j), 0x00000000); WREG32 5296 drivers/gpu/drm/radeon/cik.c WREG32((0x2c20 + j), 0x00000000); WREG32 5297 drivers/gpu/drm/radeon/cik.c WREG32((0x2c24 + j), 0x00000000); WREG32 5299 drivers/gpu/drm/radeon/cik.c WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); WREG32 5306 drivers/gpu/drm/radeon/cik.c WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); WREG32 5308 drivers/gpu/drm/radeon/cik.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 5310 drivers/gpu/drm/radeon/cik.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 5312 drivers/gpu/drm/radeon/cik.c WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, WREG32 5316 drivers/gpu/drm/radeon/cik.c WREG32(MC_VM_FB_LOCATION, tmp); WREG32 5318 drivers/gpu/drm/radeon/cik.c WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); WREG32 5319 drivers/gpu/drm/radeon/cik.c WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); WREG32 5320 drivers/gpu/drm/radeon/cik.c WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); WREG32 5321 drivers/gpu/drm/radeon/cik.c WREG32(MC_VM_AGP_BASE, 0); WREG32 5322 drivers/gpu/drm/radeon/cik.c WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); WREG32 5323 drivers/gpu/drm/radeon/cik.c WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); WREG32 5416 drivers/gpu/drm/radeon/cik.c WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); WREG32 5419 drivers/gpu/drm/radeon/cik.c WREG32(VM_INVALIDATE_REQUEST, 0x1); WREG32 5445 drivers/gpu/drm/radeon/cik.c WREG32(MC_VM_MX_L1_TLB_CNTL, WREG32 5453 drivers/gpu/drm/radeon/cik.c WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | WREG32 5459 drivers/gpu/drm/radeon/cik.c WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); WREG32 5460 drivers/gpu/drm/radeon/cik.c WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | WREG32 5464 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); WREG32 5465 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); WREG32 5466 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); WREG32 5467 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 5469 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT0_CNTL2, 0); WREG32 5470 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | WREG32 5473 drivers/gpu/drm/radeon/cik.c WREG32(0x15D4, 0); WREG32 5474 drivers/gpu/drm/radeon/cik.c WREG32(0x15D8, 0); WREG32 5475 drivers/gpu/drm/radeon/cik.c WREG32(0x15DC, 0); WREG32 5479 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); WREG32 5480 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); WREG32 5483 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), WREG32 5486 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), WREG32 5491 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 5493 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT1_CNTL2, 4); WREG32 5494 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | WREG32 5512 drivers/gpu/drm/radeon/cik.c WREG32(CHUB_CONTROL, tmp); WREG32 5521 drivers/gpu/drm/radeon/cik.c WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT); WREG32 5522 drivers/gpu/drm/radeon/cik.c WREG32(SH_MEM_APE1_BASE, 1); WREG32 5523 drivers/gpu/drm/radeon/cik.c WREG32(SH_MEM_APE1_LIMIT, 0); WREG32 5524 drivers/gpu/drm/radeon/cik.c WREG32(SH_MEM_BASES, 0); WREG32 5526 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0); WREG32 5527 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0); WREG32 5528 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0); WREG32 5529 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); WREG32 5564 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT0_CNTL, 0); WREG32 5565 drivers/gpu/drm/radeon/cik.c WREG32(VM_CONTEXT1_CNTL, 0); WREG32 5567 drivers/gpu/drm/radeon/cik.c WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | WREG32 5570 drivers/gpu/drm/radeon/cik.c WREG32(VM_L2_CNTL, WREG32 5576 drivers/gpu/drm/radeon/cik.c WREG32(VM_L2_CNTL2, 0); WREG32 5577 drivers/gpu/drm/radeon/cik.c WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | WREG32 5781 drivers/gpu/drm/radeon/cik.c WREG32(CP_INT_CNTL_RING0, tmp); WREG32 5793 drivers/gpu/drm/radeon/cik.c WREG32(RLC_LB_CNTL, tmp); WREG32 5827 drivers/gpu/drm/radeon/cik.c WREG32(RLC_CNTL, rlc); WREG32 5840 drivers/gpu/drm/radeon/cik.c WREG32(RLC_CNTL, data); WREG32 5859 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPR_REG2, tmp); WREG32 5880 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPR_REG2, tmp); WREG32 5892 drivers/gpu/drm/radeon/cik.c WREG32(RLC_CNTL, 0); WREG32 5908 drivers/gpu/drm/radeon/cik.c WREG32(RLC_CNTL, RLC_ENABLE); WREG32 5935 drivers/gpu/drm/radeon/cik.c WREG32(RLC_CGCG_CGLS_CTRL, tmp); WREG32 5943 drivers/gpu/drm/radeon/cik.c WREG32(RLC_LB_CNTR_INIT, 0); WREG32 5944 drivers/gpu/drm/radeon/cik.c WREG32(RLC_LB_CNTR_MAX, 0x00008000); WREG32 5947 drivers/gpu/drm/radeon/cik.c WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); WREG32 5948 drivers/gpu/drm/radeon/cik.c WREG32(RLC_LB_PARAMS, 0x00600408); WREG32 5949 drivers/gpu/drm/radeon/cik.c WREG32(RLC_LB_CNTL, 0x80000004); WREG32 5951 drivers/gpu/drm/radeon/cik.c WREG32(RLC_MC_CNTL, 0); WREG32 5952 drivers/gpu/drm/radeon/cik.c WREG32(RLC_UCODE_CNTL, 0); WREG32 5963 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_UCODE_ADDR, 0); WREG32 5965 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 5966 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version)); WREG32 5988 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_UCODE_ADDR, 0); WREG32 5990 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 5991 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_UCODE_ADDR, 0); WREG32 5998 drivers/gpu/drm/radeon/cik.c WREG32(RLC_DRIVER_DMA_STATUS, 0); WREG32 6017 drivers/gpu/drm/radeon/cik.c WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); WREG32 6018 drivers/gpu/drm/radeon/cik.c WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); WREG32 6020 drivers/gpu/drm/radeon/cik.c WREG32(RLC_SERDES_WR_CTRL, tmp2); WREG32 6037 drivers/gpu/drm/radeon/cik.c WREG32(RLC_CGCG_CGLS_CTRL, data); WREG32 6051 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEM_SLP_CNTL, data); WREG32 6059 drivers/gpu/drm/radeon/cik.c WREG32(RLC_CGTT_MGCG_OVERRIDE, data); WREG32 6064 drivers/gpu/drm/radeon/cik.c WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); WREG32 6065 drivers/gpu/drm/radeon/cik.c WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); WREG32 6067 drivers/gpu/drm/radeon/cik.c WREG32(RLC_SERDES_WR_CTRL, data); WREG32 6084 drivers/gpu/drm/radeon/cik.c WREG32(CGTS_SM_CTRL_REG, data); WREG32 6090 drivers/gpu/drm/radeon/cik.c WREG32(RLC_CGTT_MGCG_OVERRIDE, data); WREG32 6095 drivers/gpu/drm/radeon/cik.c WREG32(RLC_MEM_SLP_CNTL, data); WREG32 6101 drivers/gpu/drm/radeon/cik.c WREG32(CP_MEM_SLP_CNTL, data); WREG32 6107 drivers/gpu/drm/radeon/cik.c WREG32(CGTS_SM_CTRL_REG, data); WREG32 6112 drivers/gpu/drm/radeon/cik.c WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); WREG32 6113 drivers/gpu/drm/radeon/cik.c WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); WREG32 6115 drivers/gpu/drm/radeon/cik.c WREG32(RLC_SERDES_WR_CTRL, data); WREG32 6147 drivers/gpu/drm/radeon/cik.c WREG32(mc_cg_registers[i], data); WREG32 6164 drivers/gpu/drm/radeon/cik.c WREG32(mc_cg_registers[i], data); WREG32 6174 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); WREG32 6175 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); WREG32 6180 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); WREG32 6185 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); WREG32 6198 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); WREG32 6203 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); WREG32 6208 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); WREG32 6213 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); WREG32 6230 drivers/gpu/drm/radeon/cik.c WREG32(UVD_CGC_CTRL, data); WREG32 6239 drivers/gpu/drm/radeon/cik.c WREG32(UVD_CGC_CTRL, data); WREG32 6274 drivers/gpu/drm/radeon/cik.c WREG32(HDP_HOST_PATH_CNTL, data); WREG32 6290 drivers/gpu/drm/radeon/cik.c WREG32(HDP_MEM_POWER_LS, data); WREG32 6378 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_CNTL, data); WREG32 6392 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_CNTL, data); WREG32 6405 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_CNTL, data); WREG32 6418 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_CNTL, data); WREG32 6518 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_CNTL, data); WREG32 6523 drivers/gpu/drm/radeon/cik.c WREG32(RLC_AUTO_PG_CTRL, data); WREG32 6528 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_CNTL, data); WREG32 6533 drivers/gpu/drm/radeon/cik.c WREG32(RLC_AUTO_PG_CTRL, data); WREG32 6587 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_AO_CU_MASK, tmp); WREG32 6592 drivers/gpu/drm/radeon/cik.c WREG32(RLC_MAX_PG_CU, tmp); WREG32 6606 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_CNTL, data); WREG32 6620 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_CNTL, data); WREG32 6632 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); WREG32 6633 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); WREG32 6634 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); WREG32 6635 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size); WREG32 6637 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); WREG32 6639 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_SCRATCH_DATA, 0); WREG32 6642 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); WREG32 6644 drivers/gpu/drm/radeon/cik.c WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]); WREG32 6650 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_CNTL, data); WREG32 6652 drivers/gpu/drm/radeon/cik.c WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); WREG32 6653 drivers/gpu/drm/radeon/cik.c WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8); WREG32 6658 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB_WPTR_POLL_CNTL, data); WREG32 6661 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_DELAY, data); WREG32 6666 drivers/gpu/drm/radeon/cik.c WREG32(RLC_PG_DELAY_2, data); WREG32 6671 drivers/gpu/drm/radeon/cik.c WREG32(RLC_AUTO_PG_CTRL, data); WREG32 6834 drivers/gpu/drm/radeon/cik.c WREG32(IH_CNTL, ih_cntl); WREG32 6835 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 6853 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 6854 drivers/gpu/drm/radeon/cik.c WREG32(IH_CNTL, ih_cntl); WREG32 6856 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_RPTR, 0); WREG32 6857 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_WPTR, 0); WREG32 6876 drivers/gpu/drm/radeon/cik.c WREG32(CP_INT_CNTL_RING0, tmp); WREG32 6879 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); WREG32 6881 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); WREG32 6883 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME1_PIPE0_INT_CNTL, 0); WREG32 6884 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME1_PIPE1_INT_CNTL, 0); WREG32 6885 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME1_PIPE2_INT_CNTL, 0); WREG32 6886 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME1_PIPE3_INT_CNTL, 0); WREG32 6887 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME2_PIPE0_INT_CNTL, 0); WREG32 6888 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME2_PIPE1_INT_CNTL, 0); WREG32 6889 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME2_PIPE2_INT_CNTL, 0); WREG32 6890 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME2_PIPE3_INT_CNTL, 0); WREG32 6892 drivers/gpu/drm/radeon/cik.c WREG32(GRBM_INT_CNTL, 0); WREG32 6894 drivers/gpu/drm/radeon/cik.c WREG32(SRBM_INT_CNTL, 0); WREG32 6896 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); WREG32 6897 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); WREG32 6899 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); WREG32 6900 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); WREG32 6903 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); WREG32 6904 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); WREG32 6908 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); WREG32 6909 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); WREG32 6912 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); WREG32 6913 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); WREG32 6916 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); WREG32 6917 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); WREG32 6921 drivers/gpu/drm/radeon/cik.c WREG32(DAC_AUTODETECT_INT_CONTROL, 0); WREG32 6925 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD1_INT_CONTROL, tmp); WREG32 6927 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD2_INT_CONTROL, tmp); WREG32 6929 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD3_INT_CONTROL, tmp); WREG32 6931 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD4_INT_CONTROL, tmp); WREG32 6933 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD5_INT_CONTROL, tmp); WREG32 6935 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD6_INT_CONTROL, tmp); WREG32 6973 drivers/gpu/drm/radeon/cik.c WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); WREG32 6981 drivers/gpu/drm/radeon/cik.c WREG32(INTERRUPT_CNTL, interrupt_cntl); WREG32 6983 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); WREG32 6994 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); WREG32 6995 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); WREG32 6997 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 7000 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_RPTR, 0); WREG32 7001 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_WPTR, 0); WREG32 7008 drivers/gpu/drm/radeon/cik.c WREG32(IH_CNTL, ih_cntl); WREG32 7232 drivers/gpu/drm/radeon/cik.c WREG32(CP_INT_CNTL_RING0, cp_int_cntl); WREG32 7234 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); WREG32 7235 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); WREG32 7237 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); WREG32 7238 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1); WREG32 7239 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2); WREG32 7240 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3); WREG32 7241 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0); WREG32 7242 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1); WREG32 7243 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2); WREG32 7244 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3); WREG32 7246 drivers/gpu/drm/radeon/cik.c WREG32(GRBM_INT_CNTL, grbm_int_cntl); WREG32 7248 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); WREG32 7249 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); WREG32 7251 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); WREG32 7252 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); WREG32 7255 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); WREG32 7256 drivers/gpu/drm/radeon/cik.c WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); WREG32 7260 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, WREG32 7262 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, WREG32 7266 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, WREG32 7268 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, WREG32 7272 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, WREG32 7274 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, WREG32 7278 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD1_INT_CONTROL, hpd1); WREG32 7279 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD2_INT_CONTROL, hpd2); WREG32 7280 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD3_INT_CONTROL, hpd3); WREG32 7281 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD4_INT_CONTROL, hpd4); WREG32 7282 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD5_INT_CONTROL, hpd5); WREG32 7283 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD6_INT_CONTROL, hpd6); WREG32 7330 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, WREG32 7333 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, WREG32 7336 drivers/gpu/drm/radeon/cik.c WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); WREG32 7338 drivers/gpu/drm/radeon/cik.c WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); WREG32 7340 drivers/gpu/drm/radeon/cik.c WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); WREG32 7342 drivers/gpu/drm/radeon/cik.c WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); WREG32 7346 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, WREG32 7349 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, WREG32 7352 drivers/gpu/drm/radeon/cik.c WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); WREG32 7354 drivers/gpu/drm/radeon/cik.c WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); WREG32 7356 drivers/gpu/drm/radeon/cik.c WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); WREG32 7358 drivers/gpu/drm/radeon/cik.c WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); WREG32 7363 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, WREG32 7366 drivers/gpu/drm/radeon/cik.c WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, WREG32 7369 drivers/gpu/drm/radeon/cik.c WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); WREG32 7371 drivers/gpu/drm/radeon/cik.c WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); WREG32 7373 drivers/gpu/drm/radeon/cik.c WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); WREG32 7375 drivers/gpu/drm/radeon/cik.c WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); WREG32 7381 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD1_INT_CONTROL, tmp); WREG32 7386 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD2_INT_CONTROL, tmp); WREG32 7391 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD3_INT_CONTROL, tmp); WREG32 7396 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD4_INT_CONTROL, tmp); WREG32 7401 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD5_INT_CONTROL, tmp); WREG32 7406 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD6_INT_CONTROL, tmp); WREG32 7411 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD1_INT_CONTROL, tmp); WREG32 7416 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD2_INT_CONTROL, tmp); WREG32 7421 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD3_INT_CONTROL, tmp); WREG32 7426 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD4_INT_CONTROL, tmp); WREG32 7431 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD5_INT_CONTROL, tmp); WREG32 7436 drivers/gpu/drm/radeon/cik.c WREG32(DC_HPD6_INT_CONTROL, tmp); WREG32 7516 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_CNTL, tmp); WREG32 7903 drivers/gpu/drm/radeon/cik.c WREG32(SRBM_INT_ACK, 0x1); WREG32 8102 drivers/gpu/drm/radeon/cik.c WREG32(IH_RB_RPTR, rptr); WREG32 8805 drivers/gpu/drm/radeon/cik.c WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); WREG32 8855 drivers/gpu/drm/radeon/cik.c WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, WREG32 8858 drivers/gpu/drm/radeon/cik.c WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, WREG32 9357 drivers/gpu/drm/radeon/cik.c WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); WREG32 9358 drivers/gpu/drm/radeon/cik.c WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, WREG32 9365 drivers/gpu/drm/radeon/cik.c WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); WREG32 9366 drivers/gpu/drm/radeon/cik.c WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, WREG32 9370 drivers/gpu/drm/radeon/cik.c WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask); WREG32 9421 drivers/gpu/drm/radeon/cik.c WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); WREG32 121 drivers/gpu/drm/radeon/cik_sdma.c WREG32(reg, (ring->wptr << 2) & 0x3fffc); WREG32 266 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); WREG32 267 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); WREG32 277 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1); WREG32 280 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SRBM_SOFT_RESET, 0); WREG32 319 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_CNTL + reg_offset, value); WREG32 351 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); WREG32 384 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); WREG32 385 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); WREG32 393 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); WREG32 396 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0); WREG32 397 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0); WREG32 400 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset, WREG32 402 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset, WREG32 408 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); WREG32 409 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); WREG32 412 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); WREG32 415 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); WREG32 422 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl); WREG32 484 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); WREG32 486 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); WREG32 487 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); WREG32 493 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); WREG32 495 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); WREG32 496 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); WREG32 502 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); WREG32 504 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++)); WREG32 505 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); WREG32 509 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); WREG32 511 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); WREG32 512 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); WREG32 515 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); WREG32 516 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); WREG32 63 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(CG_BIF_REQ_AND_RSP, bif); WREG32 127 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(GRBM_GFX_INDEX, 0xC0000000); WREG32 154 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(GRBM_GFX_INDEX, 0xC0000000); WREG32 188 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(GRBM_GFX_INDEX, 0xC0000000); WREG32 196 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); WREG32 209 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(GRBM_GFX_INDEX, 0xC0000000); WREG32 217 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0); WREG32 945 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time); WREG32 1133 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_CONFIG_MCD, 0xf); WREG32 1134 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_CG_CONFIG_MCD, 0xf); WREG32 1136 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_CONFIG, 0xf); WREG32 1137 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_CG_CONFIG, 0xf); WREG32 1143 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND); WREG32 1151 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_SEQ_CG, mc_seq_cg); WREG32 1161 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_SEQ_CG, mc_seq_cg); WREG32 1174 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value); WREG32 1191 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_CONFIG_MCD, 0xf); WREG32 1192 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_CG_CONFIG_MCD, 0xf); WREG32 1194 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_CONFIG, 0xf); WREG32 1195 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_CG_CONFIG, 0xf); WREG32 1201 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND); WREG32 1209 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_SEQ_CG, mc_seq_cg); WREG32 1219 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(MC_SEQ_CG, mc_seq_cg); WREG32 1740 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32 1759 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32 1778 drivers/gpu/drm/radeon/cypress_dpm.c WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); WREG32 156 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); WREG32 157 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); WREG32 158 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(DCCG_AUDIO_DTO0_MODULE, clock); WREG32 159 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ WREG32 163 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); WREG32 164 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); WREG32 165 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(DCCG_AUDIO_DTO1_MODULE, clock); WREG32 166 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ WREG32 176 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset, WREG32 207 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, WREG32 211 drivers/gpu/drm/radeon/dce3_1_afmt.c WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, WREG32 39 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32 53 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32 55 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, WREG32 57 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); WREG32 119 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, WREG32 277 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(DCCG_AUDIO_DTO_SOURCE, value); WREG32 283 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); WREG32 284 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(DCCG_AUDIO_DTO0_MODULE, clock); WREG32 297 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(DCCG_AUDIO_DTO_SOURCE, value); WREG32 312 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); WREG32 313 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); WREG32 315 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); WREG32 316 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(DCCG_AUDIO_DTO1_MODULE, clock); WREG32 55 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); WREG32 66 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); WREG32 67 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CG_IND_DATA, (v)); WREG32 77 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); WREG32 88 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); WREG32 89 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); WREG32 99 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); WREG32 110 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); WREG32 111 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); WREG32 1187 drivers/gpu/drm/radeon/evergreen.c WREG32(CG_SCRATCH1, cg_scratch); WREG32 1348 drivers/gpu/drm/radeon/evergreen.c WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); WREG32 1424 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, WREG32 1426 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, WREG32 1428 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, WREG32 1684 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); WREG32 1709 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); WREG32 1786 drivers/gpu/drm/radeon/evergreen.c WREG32(DC_HPDx_CONTROL(hpd), tmp); WREG32 1815 drivers/gpu/drm/radeon/evergreen.c WREG32(DC_HPDx_CONTROL(hpd), 0); WREG32 1867 drivers/gpu/drm/radeon/evergreen.c WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); WREG32 1870 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, WREG32 2288 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); WREG32 2289 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, WREG32 2296 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); WREG32 2297 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, WREG32 2301 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); WREG32 2304 drivers/gpu/drm/radeon/evergreen.c WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); WREG32 2305 drivers/gpu/drm/radeon/evergreen.c WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); WREG32 2379 drivers/gpu/drm/radeon/evergreen.c WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); WREG32 2381 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); WREG32 2410 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | WREG32 2413 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_L2_CNTL2, 0); WREG32 2414 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); WREG32 2421 drivers/gpu/drm/radeon/evergreen.c WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); WREG32 2422 drivers/gpu/drm/radeon/evergreen.c WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); WREG32 2423 drivers/gpu/drm/radeon/evergreen.c WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); WREG32 2425 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); WREG32 2426 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); WREG32 2427 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); WREG32 2432 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); WREG32 2434 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); WREG32 2435 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); WREG32 2436 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); WREG32 2437 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); WREG32 2438 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); WREG32 2439 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); WREG32 2440 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); WREG32 2441 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | WREG32 2443 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 2445 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT1_CNTL, 0); WREG32 2460 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT0_CNTL, 0); WREG32 2461 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT1_CNTL, 0); WREG32 2464 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | WREG32 2466 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_L2_CNTL2, 0); WREG32 2467 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); WREG32 2470 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); WREG32 2471 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); WREG32 2472 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); WREG32 2473 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); WREG32 2474 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); WREG32 2475 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); WREG32 2476 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); WREG32 2493 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | WREG32 2496 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_L2_CNTL2, 0); WREG32 2497 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); WREG32 2503 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); WREG32 2504 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); WREG32 2505 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); WREG32 2506 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); WREG32 2507 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); WREG32 2508 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); WREG32 2509 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); WREG32 2510 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT0_CNTL, 0); WREG32 2511 drivers/gpu/drm/radeon/evergreen.c WREG32(VM_CONTEXT1_CNTL, 0); WREG32 2644 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_DP_VID_STREAM_CNTL + WREG32 2660 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl); WREG32 2675 drivers/gpu/drm/radeon/evergreen.c WREG32(VGA_RENDER_CONTROL, 0); WREG32 2686 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 2688 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); WREG32 2689 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 2695 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 2697 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); WREG32 2698 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 2720 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 2723 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); WREG32 2724 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 2737 drivers/gpu/drm/radeon/evergreen.c WREG32(BIF_FB_EN, 0); WREG32 2740 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); WREG32 2751 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); WREG32 2756 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); WREG32 2769 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], WREG32 2771 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], WREG32 2773 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], WREG32 2775 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], WREG32 2780 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); WREG32 2781 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); WREG32 2790 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); WREG32 2795 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); WREG32 2800 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); WREG32 2814 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); WREG32 2816 drivers/gpu/drm/radeon/evergreen.c WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); WREG32 2823 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 2824 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); WREG32 2825 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 2829 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 2830 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); WREG32 2831 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 2844 drivers/gpu/drm/radeon/evergreen.c WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); WREG32 2846 drivers/gpu/drm/radeon/evergreen.c WREG32(VGA_RENDER_CONTROL, save->vga_render_control); WREG32 2858 drivers/gpu/drm/radeon/evergreen.c WREG32((0x2c14 + j), 0x00000000); WREG32 2859 drivers/gpu/drm/radeon/evergreen.c WREG32((0x2c18 + j), 0x00000000); WREG32 2860 drivers/gpu/drm/radeon/evergreen.c WREG32((0x2c1c + j), 0x00000000); WREG32 2861 drivers/gpu/drm/radeon/evergreen.c WREG32((0x2c20 + j), 0x00000000); WREG32 2862 drivers/gpu/drm/radeon/evergreen.c WREG32((0x2c24 + j), 0x00000000); WREG32 2864 drivers/gpu/drm/radeon/evergreen.c WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); WREG32 2871 drivers/gpu/drm/radeon/evergreen.c WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); WREG32 2876 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 2878 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 2882 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 2884 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 2888 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 2890 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 2893 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); WREG32 2901 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_FUS_VM_FB_OFFSET, tmp); WREG32 2905 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_FB_LOCATION, tmp); WREG32 2906 drivers/gpu/drm/radeon/evergreen.c WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); WREG32 2907 drivers/gpu/drm/radeon/evergreen.c WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); WREG32 2908 drivers/gpu/drm/radeon/evergreen.c WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); WREG32 2910 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); WREG32 2911 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); WREG32 2912 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); WREG32 2914 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_AGP_BASE, 0); WREG32 2915 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); WREG32 2916 drivers/gpu/drm/radeon/evergreen.c WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); WREG32 2974 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_CNTL, WREG32 2981 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 2983 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 2984 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 2987 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 2989 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); WREG32 2991 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 2992 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 2993 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_ME_RAM_RADDR, 0); WREG32 3018 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_ME_CNTL, cp_me); WREG32 3071 drivers/gpu/drm/radeon/evergreen.c WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | WREG32 3079 drivers/gpu/drm/radeon/evergreen.c WREG32(GRBM_SOFT_RESET, 0); WREG32 3088 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_CNTL, tmp); WREG32 3089 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_SEM_WAIT_TIMER, 0x0); WREG32 3090 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); WREG32 3093 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_WPTR_DELAY, 0); WREG32 3096 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); WREG32 3097 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_RPTR_WR, 0); WREG32 3099 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_WPTR, ring->wptr); WREG32 3102 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_RPTR_ADDR, WREG32 3104 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); WREG32 3105 drivers/gpu/drm/radeon/evergreen.c WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); WREG32 3108 drivers/gpu/drm/radeon/evergreen.c WREG32(SCRATCH_UMSK, 0xff); WREG32 3111 drivers/gpu/drm/radeon/evergreen.c WREG32(SCRATCH_UMSK, 0); WREG32 3115 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_CNTL, tmp); WREG32 3117 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_BASE, ring->gpu_addr >> 8); WREG32 3118 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); WREG32 3387 drivers/gpu/drm/radeon/evergreen.c WREG32((0x2c14 + j), 0x00000000); WREG32 3388 drivers/gpu/drm/radeon/evergreen.c WREG32((0x2c18 + j), 0x00000000); WREG32 3389 drivers/gpu/drm/radeon/evergreen.c WREG32((0x2c1c + j), 0x00000000); WREG32 3390 drivers/gpu/drm/radeon/evergreen.c WREG32((0x2c20 + j), 0x00000000); WREG32 3391 drivers/gpu/drm/radeon/evergreen.c WREG32((0x2c24 + j), 0x00000000); WREG32 3394 drivers/gpu/drm/radeon/evergreen.c WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); WREG32 3395 drivers/gpu/drm/radeon/evergreen.c WREG32(SRBM_INT_CNTL, 0x1); WREG32 3396 drivers/gpu/drm/radeon/evergreen.c WREG32(SRBM_INT_ACK, 0x1); WREG32 3465 drivers/gpu/drm/radeon/evergreen.c WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); WREG32 3466 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); WREG32 3486 drivers/gpu/drm/radeon/evergreen.c WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); WREG32 3487 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); WREG32 3495 drivers/gpu/drm/radeon/evergreen.c WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); WREG32 3496 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); WREG32 3498 drivers/gpu/drm/radeon/evergreen.c WREG32(GB_ADDR_CONFIG, gb_addr_config); WREG32 3499 drivers/gpu/drm/radeon/evergreen.c WREG32(DMIF_ADDR_CONFIG, gb_addr_config); WREG32 3500 drivers/gpu/drm/radeon/evergreen.c WREG32(HDP_ADDR_CONFIG, gb_addr_config); WREG32 3501 drivers/gpu/drm/radeon/evergreen.c WREG32(DMA_TILING_CONFIG, gb_addr_config); WREG32 3502 drivers/gpu/drm/radeon/evergreen.c WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); WREG32 3503 drivers/gpu/drm/radeon/evergreen.c WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); WREG32 3504 drivers/gpu/drm/radeon/evergreen.c WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); WREG32 3521 drivers/gpu/drm/radeon/evergreen.c WREG32(GB_BACKEND_MAP, tmp); WREG32 3523 drivers/gpu/drm/radeon/evergreen.c WREG32(CGTS_SYS_TCC_DISABLE, 0); WREG32 3524 drivers/gpu/drm/radeon/evergreen.c WREG32(CGTS_TCC_DISABLE, 0); WREG32 3525 drivers/gpu/drm/radeon/evergreen.c WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); WREG32 3526 drivers/gpu/drm/radeon/evergreen.c WREG32(CGTS_USER_TCC_DISABLE, 0); WREG32 3529 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | WREG32 3532 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); WREG32 3534 drivers/gpu/drm/radeon/evergreen.c WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | WREG32 3541 drivers/gpu/drm/radeon/evergreen.c WREG32(SX_DEBUG_1, sx_debug_1); WREG32 3547 drivers/gpu/drm/radeon/evergreen.c WREG32(SMX_DC_CTL0, smx_dc_ctl0); WREG32 3550 drivers/gpu/drm/radeon/evergreen.c WREG32(SMX_SAR_CTL0, 0x00010000); WREG32 3552 drivers/gpu/drm/radeon/evergreen.c WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | WREG32 3556 drivers/gpu/drm/radeon/evergreen.c WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | WREG32 3560 drivers/gpu/drm/radeon/evergreen.c WREG32(VGT_NUM_INSTANCES, 1); WREG32 3561 drivers/gpu/drm/radeon/evergreen.c WREG32(SPI_CONFIG_CNTL, 0); WREG32 3562 drivers/gpu/drm/radeon/evergreen.c WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); WREG32 3563 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_PERFMON_CNTL, 0); WREG32 3565 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | WREG32 3631 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_CONFIG, sq_config); WREG32 3632 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); WREG32 3633 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); WREG32 3634 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); WREG32 3635 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); WREG32 3636 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); WREG32 3637 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); WREG32 3638 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); WREG32 3639 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); WREG32 3640 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); WREG32 3641 drivers/gpu/drm/radeon/evergreen.c WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); WREG32 3643 drivers/gpu/drm/radeon/evergreen.c WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | WREG32 3659 drivers/gpu/drm/radeon/evergreen.c WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); WREG32 3661 drivers/gpu/drm/radeon/evergreen.c WREG32(VGT_GS_VERTEX_REUSE, 16); WREG32 3662 drivers/gpu/drm/radeon/evergreen.c WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); WREG32 3663 drivers/gpu/drm/radeon/evergreen.c WREG32(PA_SC_LINE_STIPPLE_STATE, 0); WREG32 3665 drivers/gpu/drm/radeon/evergreen.c WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); WREG32 3666 drivers/gpu/drm/radeon/evergreen.c WREG32(VGT_OUT_DEALLOC_CNTL, 16); WREG32 3668 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_PERF_CTR0_SEL_0, 0); WREG32 3669 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_PERF_CTR0_SEL_1, 0); WREG32 3670 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_PERF_CTR1_SEL_0, 0); WREG32 3671 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_PERF_CTR1_SEL_1, 0); WREG32 3672 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_PERF_CTR2_SEL_0, 0); WREG32 3673 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_PERF_CTR2_SEL_1, 0); WREG32 3674 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_PERF_CTR3_SEL_0, 0); WREG32 3675 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_PERF_CTR3_SEL_1, 0); WREG32 3678 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR0_BASE, 0); WREG32 3679 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR1_BASE, 0); WREG32 3680 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR2_BASE, 0); WREG32 3681 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR3_BASE, 0); WREG32 3682 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR4_BASE, 0); WREG32 3683 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR5_BASE, 0); WREG32 3684 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR6_BASE, 0); WREG32 3685 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR7_BASE, 0); WREG32 3686 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR8_BASE, 0); WREG32 3687 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR9_BASE, 0); WREG32 3688 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR10_BASE, 0); WREG32 3689 drivers/gpu/drm/radeon/evergreen.c WREG32(CB_COLOR11_BASE, 0); WREG32 3693 drivers/gpu/drm/radeon/evergreen.c WREG32(i, 0); WREG32 3695 drivers/gpu/drm/radeon/evergreen.c WREG32(i, 0); WREG32 3699 drivers/gpu/drm/radeon/evergreen.c WREG32(HDP_MISC_CNTL, tmp); WREG32 3702 drivers/gpu/drm/radeon/evergreen.c WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); WREG32 3704 drivers/gpu/drm/radeon/evergreen.c WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); WREG32 3909 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); WREG32 3915 drivers/gpu/drm/radeon/evergreen.c WREG32(DMA_RB_CNTL, tmp); WREG32 3976 drivers/gpu/drm/radeon/evergreen.c WREG32(GRBM_SOFT_RESET, tmp); WREG32 3982 drivers/gpu/drm/radeon/evergreen.c WREG32(GRBM_SOFT_RESET, tmp); WREG32 3990 drivers/gpu/drm/radeon/evergreen.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 3996 drivers/gpu/drm/radeon/evergreen.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 4019 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); WREG32 4024 drivers/gpu/drm/radeon/evergreen.c WREG32(DMA_RB_CNTL, tmp); WREG32 4378 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_CNTL, mask); WREG32 4391 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_HB_CNTL, 0); WREG32 4402 drivers/gpu/drm/radeon/evergreen.c WREG32(TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK, always_on_bitmap); WREG32 4403 drivers/gpu/drm/radeon/evergreen.c WREG32(TN_RLC_LB_PARAMS, 0x00601004); WREG32 4404 drivers/gpu/drm/radeon/evergreen.c WREG32(TN_RLC_LB_INIT_SIMD_MASK, 0xffffffff); WREG32 4405 drivers/gpu/drm/radeon/evergreen.c WREG32(TN_RLC_LB_CNTR_INIT, 0x00000000); WREG32 4406 drivers/gpu/drm/radeon/evergreen.c WREG32(TN_RLC_LB_CNTR_MAX, 0x00002000); WREG32 4409 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_HB_WPTR_LSB_ADDR, 0); WREG32 4410 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_HB_WPTR_MSB_ADDR, 0); WREG32 4412 drivers/gpu/drm/radeon/evergreen.c WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); WREG32 4413 drivers/gpu/drm/radeon/evergreen.c WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); WREG32 4415 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_HB_BASE, 0); WREG32 4416 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_HB_RPTR, 0); WREG32 4417 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_HB_WPTR, 0); WREG32 4418 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_HB_WPTR_LSB_ADDR, 0); WREG32 4419 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_HB_WPTR_MSB_ADDR, 0); WREG32 4421 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_MC_CNTL, 0); WREG32 4422 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_UCODE_CNTL, 0); WREG32 4427 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_UCODE_ADDR, i); WREG32 4428 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 4432 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_UCODE_ADDR, i); WREG32 4433 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 4437 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_UCODE_ADDR, i); WREG32 4438 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 4441 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_UCODE_ADDR, 0); WREG32 4469 drivers/gpu/drm/radeon/evergreen.c WREG32(CAYMAN_DMA1_CNTL, tmp); WREG32 4471 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); WREG32 4473 drivers/gpu/drm/radeon/evergreen.c WREG32(DMA_CNTL, tmp); WREG32 4474 drivers/gpu/drm/radeon/evergreen.c WREG32(GRBM_INT_CNTL, 0); WREG32 4475 drivers/gpu/drm/radeon/evergreen.c WREG32(SRBM_INT_CNTL, 0); WREG32 4477 drivers/gpu/drm/radeon/evergreen.c WREG32(INT_MASK + crtc_offsets[i], 0); WREG32 4479 drivers/gpu/drm/radeon/evergreen.c WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); WREG32 4483 drivers/gpu/drm/radeon/evergreen.c WREG32(DACA_AUTODETECT_INT_CONTROL, 0); WREG32 4484 drivers/gpu/drm/radeon/evergreen.c WREG32(DACB_AUTODETECT_INT_CONTROL, 0); WREG32 4566 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_INT_CNTL, cp_int_cntl); WREG32 4568 drivers/gpu/drm/radeon/evergreen.c WREG32(DMA_CNTL, dma_cntl); WREG32 4571 drivers/gpu/drm/radeon/evergreen.c WREG32(CAYMAN_DMA1_CNTL, dma_cntl1); WREG32 4573 drivers/gpu/drm/radeon/evergreen.c WREG32(GRBM_INT_CNTL, grbm_int_cntl); WREG32 4584 drivers/gpu/drm/radeon/evergreen.c WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); WREG32 4594 drivers/gpu/drm/radeon/evergreen.c WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int); WREG32 4596 drivers/gpu/drm/radeon/evergreen.c WREG32(CG_THERMAL_INT, thermal_int); WREG32 4630 drivers/gpu/drm/radeon/evergreen.c WREG32(GRPH_INT_STATUS + crtc_offsets[j], WREG32 4636 drivers/gpu/drm/radeon/evergreen.c WREG32(VBLANK_STATUS + crtc_offsets[j], WREG32 4639 drivers/gpu/drm/radeon/evergreen.c WREG32(VLINE_STATUS + crtc_offsets[j], WREG32 4696 drivers/gpu/drm/radeon/evergreen.c WREG32(IH_RB_CNTL, tmp); WREG32 4836 drivers/gpu/drm/radeon/evergreen.c WREG32(SRBM_INT_ACK, 0x1); WREG32 4911 drivers/gpu/drm/radeon/evergreen.c WREG32(IH_RB_RPTR, rptr); WREG32 64 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(AZ_HOT_PLUG_CONTROL, tmp); WREG32 80 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_PACKET_CONTROL + offset, WREG32 83 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_PACKET_CONTROL + offset, WREG32 87 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); WREG32 88 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); WREG32 90 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); WREG32 91 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); WREG32 93 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); WREG32 94 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); WREG32 213 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(AFMT_AVI_INFO0 + offset, WREG32 215 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(AFMT_AVI_INFO1 + offset, WREG32 217 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(AFMT_AVI_INFO2 + offset, WREG32 219 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(AFMT_AVI_INFO3 + offset, WREG32 252 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(DCCG_AUDIO_DTO0_CNTL, value); WREG32 260 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(DCCG_AUDIO_DTO_SOURCE, value); WREG32 266 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); WREG32 267 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(DCCG_AUDIO_DTO0_MODULE, clock); WREG32 277 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(DCCG_AUDIO_DTO1_CNTL, value); WREG32 286 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(DCCG_AUDIO_DTO_SOURCE, value); WREG32 302 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); WREG32 303 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(DCCG_AUDIO_DTO1_MODULE, clock); WREG32 311 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_VBI_PACKET_CONTROL + offset, WREG32 351 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_CONTROL + offset, val); WREG32 359 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(AFMT_INFOFRAME_CONTROL0 + offset, WREG32 362 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(AFMT_60958_0 + offset, WREG32 365 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(AFMT_60958_1 + offset, WREG32 368 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(AFMT_60958_2 + offset, WREG32 376 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, WREG32 379 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, WREG32 414 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, WREG32 422 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, WREG32 431 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); WREG32 461 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, WREG32 474 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); WREG32 477 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, WREG32 483 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); WREG32 323 drivers/gpu/drm/radeon/kv_dpm.c WREG32(config_regs->offset << 2, data); WREG32 34 drivers/gpu/drm/radeon/kv_smc.c WREG32(SMC_MESSAGE_0, id & SMC_MSG_MASK); WREG32 69 drivers/gpu/drm/radeon/kv_smc.c WREG32(SMC_MSG_ARG_0, parameter); WREG32 82 drivers/gpu/drm/radeon/kv_smc.c WREG32(SMC_IND_INDEX_0, smc_address); WREG32 164 drivers/gpu/drm/radeon/kv_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 177 drivers/gpu/drm/radeon/kv_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 210 drivers/gpu/drm/radeon/kv_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 51 drivers/gpu/drm/radeon/ni.c WREG32(TN_SMC_IND_INDEX_0, (reg)); WREG32 62 drivers/gpu/drm/radeon/ni.c WREG32(TN_SMC_IND_INDEX_0, (reg)); WREG32 63 drivers/gpu/drm/radeon/ni.c WREG32(TN_SMC_IND_DATA_0, (v)); WREG32 677 drivers/gpu/drm/radeon/ni.c WREG32(MC_SHARED_BLACKOUT_CNTL, 1); WREG32 681 drivers/gpu/drm/radeon/ni.c WREG32(MC_SEQ_SUP_CNTL, 0x00000008); WREG32 682 drivers/gpu/drm/radeon/ni.c WREG32(MC_SEQ_SUP_CNTL, 0x00000010); WREG32 686 drivers/gpu/drm/radeon/ni.c WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); WREG32 687 drivers/gpu/drm/radeon/ni.c WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); WREG32 692 drivers/gpu/drm/radeon/ni.c WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); WREG32 695 drivers/gpu/drm/radeon/ni.c WREG32(MC_SEQ_SUP_CNTL, 0x00000008); WREG32 696 drivers/gpu/drm/radeon/ni.c WREG32(MC_SEQ_SUP_CNTL, 0x00000004); WREG32 697 drivers/gpu/drm/radeon/ni.c WREG32(MC_SEQ_SUP_CNTL, 0x00000001); WREG32 707 drivers/gpu/drm/radeon/ni.c WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); WREG32 1006 drivers/gpu/drm/radeon/ni.c WREG32((0x2c14 + j), 0x00000000); WREG32 1007 drivers/gpu/drm/radeon/ni.c WREG32((0x2c18 + j), 0x00000000); WREG32 1008 drivers/gpu/drm/radeon/ni.c WREG32((0x2c1c + j), 0x00000000); WREG32 1009 drivers/gpu/drm/radeon/ni.c WREG32((0x2c20 + j), 0x00000000); WREG32 1010 drivers/gpu/drm/radeon/ni.c WREG32((0x2c24 + j), 0x00000000); WREG32 1013 drivers/gpu/drm/radeon/ni.c WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); WREG32 1014 drivers/gpu/drm/radeon/ni.c WREG32(SRBM_INT_CNTL, 0x1); WREG32 1015 drivers/gpu/drm/radeon/ni.c WREG32(SRBM_INT_ACK, 0x1); WREG32 1095 drivers/gpu/drm/radeon/ni.c WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); WREG32 1096 drivers/gpu/drm/radeon/ni.c WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); WREG32 1115 drivers/gpu/drm/radeon/ni.c WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); WREG32 1116 drivers/gpu/drm/radeon/ni.c WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); WREG32 1124 drivers/gpu/drm/radeon/ni.c WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); WREG32 1125 drivers/gpu/drm/radeon/ni.c WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); WREG32 1127 drivers/gpu/drm/radeon/ni.c WREG32(GB_ADDR_CONFIG, gb_addr_config); WREG32 1128 drivers/gpu/drm/radeon/ni.c WREG32(DMIF_ADDR_CONFIG, gb_addr_config); WREG32 1130 drivers/gpu/drm/radeon/ni.c WREG32(DMIF_ADDR_CALC, gb_addr_config); WREG32 1131 drivers/gpu/drm/radeon/ni.c WREG32(HDP_ADDR_CONFIG, gb_addr_config); WREG32 1132 drivers/gpu/drm/radeon/ni.c WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); WREG32 1133 drivers/gpu/drm/radeon/ni.c WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); WREG32 1134 drivers/gpu/drm/radeon/ni.c WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); WREG32 1135 drivers/gpu/drm/radeon/ni.c WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); WREG32 1136 drivers/gpu/drm/radeon/ni.c WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); WREG32 1155 drivers/gpu/drm/radeon/ni.c WREG32(GB_BACKEND_MAP, tmp); WREG32 1160 drivers/gpu/drm/radeon/ni.c WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); WREG32 1161 drivers/gpu/drm/radeon/ni.c WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); WREG32 1162 drivers/gpu/drm/radeon/ni.c WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); WREG32 1163 drivers/gpu/drm/radeon/ni.c WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); WREG32 1168 drivers/gpu/drm/radeon/ni.c WREG32(CGTS_SM_CTRL_REG, OVERRIDE); WREG32 1169 drivers/gpu/drm/radeon/ni.c WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); WREG32 1172 drivers/gpu/drm/radeon/ni.c WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); WREG32 1176 drivers/gpu/drm/radeon/ni.c WREG32(SX_DEBUG_1, sx_debug_1); WREG32 1181 drivers/gpu/drm/radeon/ni.c WREG32(SMX_DC_CTL0, smx_dc_ctl0); WREG32 1183 drivers/gpu/drm/radeon/ni.c WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); WREG32 1186 drivers/gpu/drm/radeon/ni.c WREG32(VGT_OFFCHIP_LDS_BASE, 0); WREG32 1187 drivers/gpu/drm/radeon/ni.c WREG32(SQ_LSTMP_RING_BASE, 0); WREG32 1188 drivers/gpu/drm/radeon/ni.c WREG32(SQ_HSTMP_RING_BASE, 0); WREG32 1189 drivers/gpu/drm/radeon/ni.c WREG32(SQ_ESTMP_RING_BASE, 0); WREG32 1190 drivers/gpu/drm/radeon/ni.c WREG32(SQ_GSTMP_RING_BASE, 0); WREG32 1191 drivers/gpu/drm/radeon/ni.c WREG32(SQ_VSTMP_RING_BASE, 0); WREG32 1192 drivers/gpu/drm/radeon/ni.c WREG32(SQ_PSTMP_RING_BASE, 0); WREG32 1194 drivers/gpu/drm/radeon/ni.c WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); WREG32 1196 drivers/gpu/drm/radeon/ni.c WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) | WREG32 1200 drivers/gpu/drm/radeon/ni.c WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | WREG32 1205 drivers/gpu/drm/radeon/ni.c WREG32(VGT_NUM_INSTANCES, 1); WREG32 1207 drivers/gpu/drm/radeon/ni.c WREG32(CP_PERFMON_CNTL, 0); WREG32 1209 drivers/gpu/drm/radeon/ni.c WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | WREG32 1214 drivers/gpu/drm/radeon/ni.c WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); WREG32 1215 drivers/gpu/drm/radeon/ni.c WREG32(SQ_CONFIG, (VC_ENABLE | WREG32 1220 drivers/gpu/drm/radeon/ni.c WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); WREG32 1222 drivers/gpu/drm/radeon/ni.c WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | WREG32 1225 drivers/gpu/drm/radeon/ni.c WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | WREG32 1228 drivers/gpu/drm/radeon/ni.c WREG32(VGT_GS_VERTEX_REUSE, 16); WREG32 1229 drivers/gpu/drm/radeon/ni.c WREG32(PA_SC_LINE_STIPPLE_STATE, 0); WREG32 1231 drivers/gpu/drm/radeon/ni.c WREG32(CB_PERF_CTR0_SEL_0, 0); WREG32 1232 drivers/gpu/drm/radeon/ni.c WREG32(CB_PERF_CTR0_SEL_1, 0); WREG32 1233 drivers/gpu/drm/radeon/ni.c WREG32(CB_PERF_CTR1_SEL_0, 0); WREG32 1234 drivers/gpu/drm/radeon/ni.c WREG32(CB_PERF_CTR1_SEL_1, 0); WREG32 1235 drivers/gpu/drm/radeon/ni.c WREG32(CB_PERF_CTR2_SEL_0, 0); WREG32 1236 drivers/gpu/drm/radeon/ni.c WREG32(CB_PERF_CTR2_SEL_1, 0); WREG32 1237 drivers/gpu/drm/radeon/ni.c WREG32(CB_PERF_CTR3_SEL_0, 0); WREG32 1238 drivers/gpu/drm/radeon/ni.c WREG32(CB_PERF_CTR3_SEL_1, 0); WREG32 1242 drivers/gpu/drm/radeon/ni.c WREG32(HDP_MISC_CNTL, tmp); WREG32 1245 drivers/gpu/drm/radeon/ni.c WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); WREG32 1247 drivers/gpu/drm/radeon/ni.c WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); WREG32 1268 drivers/gpu/drm/radeon/ni.c WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); WREG32 1271 drivers/gpu/drm/radeon/ni.c WREG32(VM_INVALIDATE_REQUEST, 1); WREG32 1286 drivers/gpu/drm/radeon/ni.c WREG32(MC_VM_MX_L1_TLB_CNTL, WREG32 1294 drivers/gpu/drm/radeon/ni.c WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | WREG32 1300 drivers/gpu/drm/radeon/ni.c WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); WREG32 1301 drivers/gpu/drm/radeon/ni.c WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | WREG32 1305 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); WREG32 1306 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); WREG32 1307 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); WREG32 1308 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 1310 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT0_CNTL2, 0); WREG32 1311 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | WREG32 1314 drivers/gpu/drm/radeon/ni.c WREG32(0x15D4, 0); WREG32 1315 drivers/gpu/drm/radeon/ni.c WREG32(0x15D8, 0); WREG32 1316 drivers/gpu/drm/radeon/ni.c WREG32(0x15DC, 0); WREG32 1324 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); WREG32 1325 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), WREG32 1327 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), WREG32 1332 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 1334 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT1_CNTL2, 4); WREG32 1335 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | WREG32 1368 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT0_CNTL, 0); WREG32 1369 drivers/gpu/drm/radeon/ni.c WREG32(VM_CONTEXT1_CNTL, 0); WREG32 1371 drivers/gpu/drm/radeon/ni.c WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | WREG32 1375 drivers/gpu/drm/radeon/ni.c WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | WREG32 1379 drivers/gpu/drm/radeon/ni.c WREG32(VM_L2_CNTL2, 0); WREG32 1380 drivers/gpu/drm/radeon/ni.c WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | WREG32 1395 drivers/gpu/drm/radeon/ni.c WREG32(SRBM_GFX_CNTL, RINGID(ring)); WREG32 1396 drivers/gpu/drm/radeon/ni.c WREG32(CP_INT_CNTL, cp_int_cntl); WREG32 1464 drivers/gpu/drm/radeon/ni.c WREG32(CP_ME_CNTL, 0); WREG32 1468 drivers/gpu/drm/radeon/ni.c WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); WREG32 1469 drivers/gpu/drm/radeon/ni.c WREG32(SCRATCH_UMSK, 0); WREG32 1512 drivers/gpu/drm/radeon/ni.c WREG32(CP_RB0_WPTR, ring->wptr); WREG32 1515 drivers/gpu/drm/radeon/ni.c WREG32(CP_RB1_WPTR, ring->wptr); WREG32 1518 drivers/gpu/drm/radeon/ni.c WREG32(CP_RB2_WPTR, ring->wptr); WREG32 1534 drivers/gpu/drm/radeon/ni.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 1536 drivers/gpu/drm/radeon/ni.c WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 1537 drivers/gpu/drm/radeon/ni.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 1540 drivers/gpu/drm/radeon/ni.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 1542 drivers/gpu/drm/radeon/ni.c WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); WREG32 1544 drivers/gpu/drm/radeon/ni.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 1545 drivers/gpu/drm/radeon/ni.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 1546 drivers/gpu/drm/radeon/ni.c WREG32(CP_ME_RAM_RADDR, 0); WREG32 1665 drivers/gpu/drm/radeon/ni.c WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | WREG32 1673 drivers/gpu/drm/radeon/ni.c WREG32(GRBM_SOFT_RESET, 0); WREG32 1676 drivers/gpu/drm/radeon/ni.c WREG32(CP_SEM_WAIT_TIMER, 0x0); WREG32 1677 drivers/gpu/drm/radeon/ni.c WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); WREG32 1680 drivers/gpu/drm/radeon/ni.c WREG32(CP_RB_WPTR_DELAY, 0); WREG32 1682 drivers/gpu/drm/radeon/ni.c WREG32(CP_DEBUG, (1 << 27)); WREG32 1685 drivers/gpu/drm/radeon/ni.c WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); WREG32 1686 drivers/gpu/drm/radeon/ni.c WREG32(SCRATCH_UMSK, 0xff); WREG32 1699 drivers/gpu/drm/radeon/ni.c WREG32(cp_rb_cntl[i], rb_cntl); WREG32 1703 drivers/gpu/drm/radeon/ni.c WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); WREG32 1704 drivers/gpu/drm/radeon/ni.c WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); WREG32 1710 drivers/gpu/drm/radeon/ni.c WREG32(cp_rb_base[i], ring->gpu_addr >> 8); WREG32 1719 drivers/gpu/drm/radeon/ni.c WREG32(cp_rb_rptr[i], 0); WREG32 1720 drivers/gpu/drm/radeon/ni.c WREG32(cp_rb_wptr[i], ring->wptr); WREG32 1846 drivers/gpu/drm/radeon/ni.c WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); WREG32 1852 drivers/gpu/drm/radeon/ni.c WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); WREG32 1859 drivers/gpu/drm/radeon/ni.c WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); WREG32 1923 drivers/gpu/drm/radeon/ni.c WREG32(GRBM_SOFT_RESET, tmp); WREG32 1929 drivers/gpu/drm/radeon/ni.c WREG32(GRBM_SOFT_RESET, tmp); WREG32 1937 drivers/gpu/drm/radeon/ni.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 1943 drivers/gpu/drm/radeon/ni.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 111 drivers/gpu/drm/radeon/ni_dma.c WREG32(reg, (ring->wptr << 2) & 0x3fffc); WREG32 168 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); WREG32 173 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); WREG32 206 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); WREG32 207 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); WREG32 215 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); WREG32 218 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_RPTR + reg_offset, 0); WREG32 219 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_WPTR + reg_offset, 0); WREG32 222 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, WREG32 224 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, WREG32 230 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); WREG32 237 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_IB_CNTL + reg_offset, ib_cntl); WREG32 241 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_CNTL + reg_offset, dma_cntl); WREG32 244 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2); WREG32 246 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); WREG32 1041 drivers/gpu/drm/radeon/ni_dpm.c WREG32(SMC_SCRATCH0, parameter); WREG32 1541 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); WREG32 1542 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); WREG32 1546 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); WREG32 1547 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); WREG32 1551 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); WREG32 1552 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); WREG32 1556 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); WREG32 1557 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); WREG32 1565 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_CG_CONFIG, mc_cg_config); WREG32 2883 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); WREG32 2884 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); WREG32 2885 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); WREG32 2886 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); WREG32 2887 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); WREG32 2888 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); WREG32 2889 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); WREG32 2890 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); WREG32 2891 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); WREG32 2892 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); WREG32 2893 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); WREG32 2894 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); WREG32 2895 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); WREG32 3157 drivers/gpu/drm/radeon/ni_dpm.c WREG32(CG_CAC_CTRL, reg); WREG32 3360 drivers/gpu/drm/radeon/ni_dpm.c WREG32(SQ_CAC_THRESHOLD, reg); WREG32 3367 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_CG_CONFIG, reg); WREG32 3372 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_CG_DATAPORT, reg); WREG32 3472 drivers/gpu/drm/radeon/ni_dpm.c WREG32(CG_BIF_REQ_AND_RSP, bif); WREG32 3487 drivers/gpu/drm/radeon/ni_dpm.c WREG32(CG_BIF_REQ_AND_RSP, bif); WREG32 170 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); WREG32 182 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); WREG32 365 drivers/gpu/drm/radeon/r100.c WREG32(voltage->gpio.reg, tmp); WREG32 374 drivers/gpu/drm/radeon/r100.c WREG32(voltage->gpio.reg, tmp); WREG32 463 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CRTC2_GEN_CNTL, tmp); WREG32 467 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CRTC_GEN_CNTL, tmp); WREG32 494 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CRTC2_GEN_CNTL, tmp); WREG32 498 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CRTC_GEN_CNTL, tmp); WREG32 570 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_FP_GEN_CNTL, tmp); WREG32 578 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_FP2_GEN_CNTL, tmp); WREG32 666 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_AIC_CNTL, tmp); WREG32 668 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); WREG32 669 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); WREG32 671 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); WREG32 673 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_AIC_CNTL, tmp); WREG32 688 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); WREG32 689 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_AIC_LO_ADDR, 0); WREG32 690 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_AIC_HI_ADDR, 0); WREG32 718 drivers/gpu/drm/radeon/r100.c WREG32(R_000040_GEN_INT_CNTL, 0); WREG32 738 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_GEN_INT_CNTL, tmp); WREG32 750 drivers/gpu/drm/radeon/r100.c WREG32(R_000040_GEN_INT_CNTL, 0); WREG32 754 drivers/gpu/drm/radeon/r100.c WREG32(R_000044_GEN_INT_STATUS, tmp); WREG32 765 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_GEN_INT_STATUS, irqs); WREG32 823 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_AIC_CNTL, msi_rearm); WREG32 824 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); WREG32 827 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); WREG32 1084 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_WPTR, ring->wptr); WREG32 1100 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_ME_RAM_ADDR, 0); WREG32 1102 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_ME_RAM_DATAH, WREG32 1104 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_ME_RAM_DATAL, WREG32 1168 drivers/gpu/drm/radeon/r100.c WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); WREG32 1175 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); WREG32 1179 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); WREG32 1181 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); WREG32 1182 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_RPTR_WR, 0); WREG32 1184 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_WPTR, ring->wptr); WREG32 1187 drivers/gpu/drm/radeon/r100.c WREG32(R_00070C_CP_RB_RPTR_ADDR, WREG32 1189 drivers/gpu/drm/radeon/r100.c WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); WREG32 1192 drivers/gpu/drm/radeon/r100.c WREG32(R_000770_SCRATCH_UMSK, 0xff); WREG32 1195 drivers/gpu/drm/radeon/r100.c WREG32(R_000770_SCRATCH_UMSK, 0); WREG32 1198 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_CNTL, tmp); WREG32 1201 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_CSQ_MODE, WREG32 1204 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_WPTR_DELAY, 0); WREG32 1205 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); WREG32 1206 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); WREG32 1248 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_CSQ_MODE, 0); WREG32 1249 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_CSQ_CNTL, 0); WREG32 1250 drivers/gpu/drm/radeon/r100.c WREG32(R_000770_SCRATCH_UMSK, 0); WREG32 2536 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_BUS_CNTL, tmp); WREG32 2545 drivers/gpu/drm/radeon/r100.c WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); WREG32 2547 drivers/gpu/drm/radeon/r100.c WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); WREG32 2549 drivers/gpu/drm/radeon/r100.c WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); WREG32 2570 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_CSQ_CNTL, 0); WREG32 2572 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); WREG32 2573 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_RPTR_WR, 0); WREG32 2574 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_WPTR, 0); WREG32 2575 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_CNTL, tmp); WREG32 2580 drivers/gpu/drm/radeon/r100.c WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | WREG32 2586 drivers/gpu/drm/radeon/r100.c WREG32(R_0000F0_RBBM_SOFT_RESET, 0); WREG32 2591 drivers/gpu/drm/radeon/r100.c WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); WREG32 2594 drivers/gpu/drm/radeon/r100.c WREG32(R_0000F0_RBBM_SOFT_RESET, 0); WREG32 2619 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_OV0_SCALE_CNTL, 0); WREG32 2620 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_SUBPIC_CNTL, 0); WREG32 2621 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_VIPH_CONTROL, 0); WREG32 2622 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_I2C_CNTL_1, 0); WREG32 2623 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_DVI_I2C_CNTL_1, 0); WREG32 2624 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CAP0_TRIG_CNTL, 0); WREG32 2625 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CAP1_TRIG_CNTL, 0); WREG32 2684 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); WREG32 2685 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); WREG32 2686 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_DAC_CNTL2, dac2_cntl); WREG32 2789 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); WREG32 2798 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); WREG32 2824 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CONFIG_CNTL, temp); WREG32 2874 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); WREG32 2876 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CLOCK_CNTL_INDEX, save); WREG32 2901 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CLOCK_CNTL_DATA, v); WREG32 2935 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); WREG32 2937 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); WREG32 3003 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_CSQ_ADDR, i << 2); WREG32 3009 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_CSQ_ADDR, i << 2); WREG32 3015 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_CSQ_ADDR, i << 2); WREG32 3135 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_SURFACE0_INFO + surf_index, flags); WREG32 3136 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); WREG32 3137 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); WREG32 3144 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_SURFACE0_INFO + surf_index, 0); WREG32 3255 drivers/gpu/drm/radeon/r100.c WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); WREG32 3361 drivers/gpu/drm/radeon/r100.c WREG32(R300_MC_IND_INDEX, temp); WREG32 3521 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | WREG32 3531 drivers/gpu/drm/radeon/r100.c WREG32(RS400_DISP1_REQ_CNTL1, (temp | WREG32 3537 drivers/gpu/drm/radeon/r100.c WREG32(RS400_DMIF_MEM_CNTL1, (temp | WREG32 3613 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | WREG32 3623 drivers/gpu/drm/radeon/r100.c WREG32(RS400_DISP2_REQ_CNTL1, (temp | WREG32 3629 drivers/gpu/drm/radeon/r100.c WREG32(RS400_DISP2_REQ_CNTL2, (temp | WREG32 3633 drivers/gpu/drm/radeon/r100.c WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); WREG32 3634 drivers/gpu/drm/radeon/r100.c WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); WREG32 3635 drivers/gpu/drm/radeon/r100.c WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); WREG32 3636 drivers/gpu/drm/radeon/r100.c WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); WREG32 3663 drivers/gpu/drm/radeon/r100.c WREG32(scratch, 0xCAFEDEAD); WREG32 3719 drivers/gpu/drm/radeon/r100.c WREG32(scratch, 0xCAFEDEAD); WREG32 3777 drivers/gpu/drm/radeon/r100.c WREG32(R_000740_CP_CSQ_CNTL, 0); WREG32 3792 drivers/gpu/drm/radeon/r100.c WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); WREG32 3793 drivers/gpu/drm/radeon/r100.c WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | WREG32 3795 drivers/gpu/drm/radeon/r100.c WREG32(R_000050_CRTC_GEN_CNTL, WREG32 3798 drivers/gpu/drm/radeon/r100.c WREG32(R_000420_OV0_SCALE_CNTL, WREG32 3800 drivers/gpu/drm/radeon/r100.c WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); WREG32 3802 drivers/gpu/drm/radeon/r100.c WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | WREG32 3804 drivers/gpu/drm/radeon/r100.c WREG32(R_0003F8_CRTC2_GEN_CNTL, WREG32 3808 drivers/gpu/drm/radeon/r100.c WREG32(R_000360_CUR2_OFFSET, WREG32 3816 drivers/gpu/drm/radeon/r100.c WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); WREG32 3818 drivers/gpu/drm/radeon/r100.c WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); WREG32 3822 drivers/gpu/drm/radeon/r100.c WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); WREG32 3823 drivers/gpu/drm/radeon/r100.c WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); WREG32 3825 drivers/gpu/drm/radeon/r100.c WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); WREG32 3853 drivers/gpu/drm/radeon/r100.c WREG32(R_00014C_MC_AGP_LOCATION, WREG32 3856 drivers/gpu/drm/radeon/r100.c WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); WREG32 3858 drivers/gpu/drm/radeon/r100.c WREG32(R_00015C_AGP_BASE_2, WREG32 3861 drivers/gpu/drm/radeon/r100.c WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); WREG32 3862 drivers/gpu/drm/radeon/r100.c WREG32(R_000170_AGP_BASE, 0); WREG32 3864 drivers/gpu/drm/radeon/r100.c WREG32(R_00015C_AGP_BASE_2, 0); WREG32 3870 drivers/gpu/drm/radeon/r100.c WREG32(R_000148_MC_FB_LOCATION, WREG32 4017 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_CSQ_CNTL, 0); WREG32 4021 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_CNTL, 0); WREG32 4025 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_SCRATCH_UMSK, 0); WREG32 67 drivers/gpu/drm/radeon/r300.c WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); WREG32 78 drivers/gpu/drm/radeon/r300.c WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); WREG32 79 drivers/gpu/drm/radeon/r300.c WREG32(RADEON_PCIE_DATA, (v)); WREG32 393 drivers/gpu/drm/radeon/r300.c WREG32(R300_GB_TILE_CONFIG, gb_tile_config); WREG32 400 drivers/gpu/drm/radeon/r300.c WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); WREG32 402 drivers/gpu/drm/radeon/r300.c WREG32(R300_RB2D_DSTCACHE_MODE, WREG32 430 drivers/gpu/drm/radeon/r300.c WREG32(RADEON_CP_CSQ_CNTL, 0); WREG32 432 drivers/gpu/drm/radeon/r300.c WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); WREG32 433 drivers/gpu/drm/radeon/r300.c WREG32(RADEON_CP_RB_RPTR_WR, 0); WREG32 434 drivers/gpu/drm/radeon/r300.c WREG32(RADEON_CP_RB_WPTR, 0); WREG32 435 drivers/gpu/drm/radeon/r300.c WREG32(RADEON_CP_RB_CNTL, tmp); WREG32 440 drivers/gpu/drm/radeon/r300.c WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | WREG32 444 drivers/gpu/drm/radeon/r300.c WREG32(R_0000F0_RBBM_SOFT_RESET, 0); WREG32 453 drivers/gpu/drm/radeon/r300.c WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); WREG32 456 drivers/gpu/drm/radeon/r300.c WREG32(R_0000F0_RBBM_SOFT_RESET, 0); WREG32 1343 drivers/gpu/drm/radeon/r300.c WREG32(R_00014C_MC_AGP_LOCATION, WREG32 1346 drivers/gpu/drm/radeon/r300.c WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); WREG32 1347 drivers/gpu/drm/radeon/r300.c WREG32(R_00015C_AGP_BASE_2, WREG32 1350 drivers/gpu/drm/radeon/r300.c WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); WREG32 1351 drivers/gpu/drm/radeon/r300.c WREG32(R_000170_AGP_BASE, 0); WREG32 1352 drivers/gpu/drm/radeon/r300.c WREG32(R_00015C_AGP_BASE_2, 0); WREG32 1358 drivers/gpu/drm/radeon/r300.c WREG32(R_000148_MC_FB_LOCATION, WREG32 97 drivers/gpu/drm/radeon/r420.c WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | WREG32 132 drivers/gpu/drm/radeon/r420.c WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); WREG32 135 drivers/gpu/drm/radeon/r420.c WREG32(R300_GB_TILE_CONFIG, tmp); WREG32 141 drivers/gpu/drm/radeon/r420.c WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); WREG32 143 drivers/gpu/drm/radeon/r420.c WREG32(R300_RB2D_DSTCACHE_MODE, WREG32 171 drivers/gpu/drm/radeon/r420.c WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); WREG32 182 drivers/gpu/drm/radeon/r420.c WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | WREG32 184 drivers/gpu/drm/radeon/r420.c WREG32(R_0001FC_MC_IND_DATA, v); WREG32 79 drivers/gpu/drm/radeon/r520.c WREG32(0x4128, 0xFF); WREG32 144 drivers/gpu/drm/radeon/r520.c WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); WREG32 149 drivers/gpu/drm/radeon/r520.c WREG32(R_000134_HDP_FB_LOCATION, WREG32 126 drivers/gpu/drm/radeon/r600.c WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); WREG32 137 drivers/gpu/drm/radeon/r600.c WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); WREG32 138 drivers/gpu/drm/radeon/r600.c WREG32(R600_RCU_DATA, (v)); WREG32 148 drivers/gpu/drm/radeon/r600.c WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32 159 drivers/gpu/drm/radeon/r600.c WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32 160 drivers/gpu/drm/radeon/r600.c WREG32(R600_UVD_CTX_DATA, (v)); WREG32 346 drivers/gpu/drm/radeon/r600.c WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); WREG32 873 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD1_INT_CONTROL, tmp); WREG32 881 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD2_INT_CONTROL, tmp); WREG32 889 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD3_INT_CONTROL, tmp); WREG32 897 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD4_INT_CONTROL, tmp); WREG32 905 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD5_INT_CONTROL, tmp); WREG32 914 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD6_INT_CONTROL, tmp); WREG32 927 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); WREG32 935 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); WREG32 943 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); WREG32 975 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD1_CONTROL, tmp); WREG32 978 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD2_CONTROL, tmp); WREG32 981 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD3_CONTROL, tmp); WREG32 984 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD4_CONTROL, tmp); WREG32 988 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD5_CONTROL, tmp); WREG32 991 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD6_CONTROL, tmp); WREG32 999 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); WREG32 1002 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); WREG32 1005 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); WREG32 1029 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD1_CONTROL, 0); WREG32 1032 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD2_CONTROL, 0); WREG32 1035 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD3_CONTROL, 0); WREG32 1038 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD4_CONTROL, 0); WREG32 1042 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD5_CONTROL, 0); WREG32 1045 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD6_CONTROL, 0); WREG32 1053 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); WREG32 1056 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); WREG32 1059 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); WREG32 1090 drivers/gpu/drm/radeon/r600.c WREG32(HDP_DEBUG1, 0); WREG32 1093 drivers/gpu/drm/radeon/r600.c WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); WREG32 1095 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); WREG32 1096 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); WREG32 1097 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); WREG32 1143 drivers/gpu/drm/radeon/r600.c WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | WREG32 1146 drivers/gpu/drm/radeon/r600.c WREG32(VM_L2_CNTL2, 0); WREG32 1147 drivers/gpu/drm/radeon/r600.c WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); WREG32 1153 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); WREG32 1154 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); WREG32 1155 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); WREG32 1156 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); WREG32 1157 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); WREG32 1158 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); WREG32 1159 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); WREG32 1160 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); WREG32 1161 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); WREG32 1162 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); WREG32 1163 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); WREG32 1164 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); WREG32 1165 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); WREG32 1166 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); WREG32 1167 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); WREG32 1168 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); WREG32 1169 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); WREG32 1170 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); WREG32 1171 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); WREG32 1172 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | WREG32 1174 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 1177 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); WREG32 1194 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); WREG32 1197 drivers/gpu/drm/radeon/r600.c WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | WREG32 1199 drivers/gpu/drm/radeon/r600.c WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); WREG32 1203 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); WREG32 1204 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); WREG32 1205 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); WREG32 1206 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); WREG32 1207 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); WREG32 1208 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); WREG32 1209 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); WREG32 1210 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); WREG32 1211 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); WREG32 1212 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); WREG32 1213 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); WREG32 1214 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); WREG32 1215 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); WREG32 1216 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); WREG32 1217 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); WREG32 1218 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); WREG32 1235 drivers/gpu/drm/radeon/r600.c WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | WREG32 1238 drivers/gpu/drm/radeon/r600.c WREG32(VM_L2_CNTL2, 0); WREG32 1239 drivers/gpu/drm/radeon/r600.c WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); WREG32 1245 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); WREG32 1246 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); WREG32 1247 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); WREG32 1248 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); WREG32 1249 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); WREG32 1250 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); WREG32 1251 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); WREG32 1252 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); WREG32 1253 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); WREG32 1254 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); WREG32 1255 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); WREG32 1256 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); WREG32 1257 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); WREG32 1258 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); WREG32 1260 drivers/gpu/drm/radeon/r600.c WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); WREG32 1284 drivers/gpu/drm/radeon/r600.c WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); WREG32 1286 drivers/gpu/drm/radeon/r600.c WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); WREG32 1296 drivers/gpu/drm/radeon/r600.c WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | WREG32 1298 drivers/gpu/drm/radeon/r600.c WREG32(R_0028FC_MC_DATA, v); WREG32 1299 drivers/gpu/drm/radeon/r600.c WREG32(R_0028F8_MC_INDEX, 0x7F); WREG32 1311 drivers/gpu/drm/radeon/r600.c WREG32((0x2c14 + j), 0x00000000); WREG32 1312 drivers/gpu/drm/radeon/r600.c WREG32((0x2c18 + j), 0x00000000); WREG32 1313 drivers/gpu/drm/radeon/r600.c WREG32((0x2c1c + j), 0x00000000); WREG32 1314 drivers/gpu/drm/radeon/r600.c WREG32((0x2c20 + j), 0x00000000); WREG32 1315 drivers/gpu/drm/radeon/r600.c WREG32((0x2c24 + j), 0x00000000); WREG32 1317 drivers/gpu/drm/radeon/r600.c WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); WREG32 1324 drivers/gpu/drm/radeon/r600.c WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); WREG32 1329 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 1331 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 1335 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 1337 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 1341 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); WREG32 1342 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); WREG32 1344 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); WREG32 1347 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_FB_LOCATION, tmp); WREG32 1348 drivers/gpu/drm/radeon/r600.c WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); WREG32 1349 drivers/gpu/drm/radeon/r600.c WREG32(HDP_NONSURFACE_INFO, (2 << 7)); WREG32 1350 drivers/gpu/drm/radeon/r600.c WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); WREG32 1352 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); WREG32 1353 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); WREG32 1354 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); WREG32 1356 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_AGP_BASE, 0); WREG32 1357 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); WREG32 1358 drivers/gpu/drm/radeon/r600.c WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); WREG32 1564 drivers/gpu/drm/radeon/r600.c WREG32(R600_BIOS_3_SCRATCH, tmp); WREG32 1700 drivers/gpu/drm/radeon/r600.c WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); WREG32 1702 drivers/gpu/drm/radeon/r600.c WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); WREG32 1705 drivers/gpu/drm/radeon/r600.c WREG32(RLC_CNTL, 0); WREG32 1711 drivers/gpu/drm/radeon/r600.c WREG32(DMA_RB_CNTL, tmp); WREG32 1788 drivers/gpu/drm/radeon/r600.c WREG32(R_008020_GRBM_SOFT_RESET, tmp); WREG32 1794 drivers/gpu/drm/radeon/r600.c WREG32(R_008020_GRBM_SOFT_RESET, tmp); WREG32 1802 drivers/gpu/drm/radeon/r600.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 1808 drivers/gpu/drm/radeon/r600.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 1832 drivers/gpu/drm/radeon/r600.c WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); WREG32 1834 drivers/gpu/drm/radeon/r600.c WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); WREG32 1837 drivers/gpu/drm/radeon/r600.c WREG32(RLC_CNTL, 0); WREG32 1842 drivers/gpu/drm/radeon/r600.c WREG32(DMA_RB_CNTL, tmp); WREG32 1860 drivers/gpu/drm/radeon/r600.c WREG32(BUS_CNTL, tmp); WREG32 1870 drivers/gpu/drm/radeon/r600.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 1872 drivers/gpu/drm/radeon/r600.c WREG32(SRBM_SOFT_RESET, 0); WREG32 2077 drivers/gpu/drm/radeon/r600.c WREG32((0x2c14 + j), 0x00000000); WREG32 2078 drivers/gpu/drm/radeon/r600.c WREG32((0x2c18 + j), 0x00000000); WREG32 2079 drivers/gpu/drm/radeon/r600.c WREG32((0x2c1c + j), 0x00000000); WREG32 2080 drivers/gpu/drm/radeon/r600.c WREG32((0x2c20 + j), 0x00000000); WREG32 2081 drivers/gpu/drm/radeon/r600.c WREG32((0x2c24 + j), 0x00000000); WREG32 2084 drivers/gpu/drm/radeon/r600.c WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); WREG32 2141 drivers/gpu/drm/radeon/r600.c WREG32(GB_TILING_CONFIG, tiling_config); WREG32 2142 drivers/gpu/drm/radeon/r600.c WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); WREG32 2143 drivers/gpu/drm/radeon/r600.c WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); WREG32 2144 drivers/gpu/drm/radeon/r600.c WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); WREG32 2147 drivers/gpu/drm/radeon/r600.c WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); WREG32 2148 drivers/gpu/drm/radeon/r600.c WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); WREG32 2151 drivers/gpu/drm/radeon/r600.c WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); WREG32 2152 drivers/gpu/drm/radeon/r600.c WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); WREG32 2154 drivers/gpu/drm/radeon/r600.c WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | WREG32 2158 drivers/gpu/drm/radeon/r600.c WREG32(ARB_GDEC_RD_CNTL, 0x00000021); WREG32 2164 drivers/gpu/drm/radeon/r600.c WREG32(SX_DEBUG_1, tmp); WREG32 2172 drivers/gpu/drm/radeon/r600.c WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); WREG32 2174 drivers/gpu/drm/radeon/r600.c WREG32(DB_DEBUG, 0); WREG32 2176 drivers/gpu/drm/radeon/r600.c WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | WREG32 2179 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_MULTI_CHIP_CNTL, 0); WREG32 2180 drivers/gpu/drm/radeon/r600.c WREG32(VGT_NUM_INSTANCES, 0); WREG32 2182 drivers/gpu/drm/radeon/r600.c WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); WREG32 2183 drivers/gpu/drm/radeon/r600.c WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); WREG32 2199 drivers/gpu/drm/radeon/r600.c WREG32(SQ_MS_FIFO_SIZES, tmp); WREG32 2281 drivers/gpu/drm/radeon/r600.c WREG32(SQ_CONFIG, sq_config); WREG32 2282 drivers/gpu/drm/radeon/r600.c WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); WREG32 2283 drivers/gpu/drm/radeon/r600.c WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); WREG32 2284 drivers/gpu/drm/radeon/r600.c WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); WREG32 2285 drivers/gpu/drm/radeon/r600.c WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); WREG32 2286 drivers/gpu/drm/radeon/r600.c WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); WREG32 2292 drivers/gpu/drm/radeon/r600.c WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); WREG32 2294 drivers/gpu/drm/radeon/r600.c WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); WREG32 2298 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | WREG32 2300 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | WREG32 2304 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | WREG32 2308 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | WREG32 2313 drivers/gpu/drm/radeon/r600.c WREG32(VGT_STRMOUT_EN, 0); WREG32 2331 drivers/gpu/drm/radeon/r600.c WREG32(VGT_ES_PER_GS, 128); WREG32 2332 drivers/gpu/drm/radeon/r600.c WREG32(VGT_GS_PER_ES, tmp); WREG32 2333 drivers/gpu/drm/radeon/r600.c WREG32(VGT_GS_PER_VS, 2); WREG32 2334 drivers/gpu/drm/radeon/r600.c WREG32(VGT_GS_VERTEX_REUSE, 16); WREG32 2337 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_LINE_STIPPLE_STATE, 0); WREG32 2338 drivers/gpu/drm/radeon/r600.c WREG32(VGT_STRMOUT_EN, 0); WREG32 2339 drivers/gpu/drm/radeon/r600.c WREG32(SX_MISC, 0); WREG32 2340 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_MODE_CNTL, 0); WREG32 2341 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_AA_CONFIG, 0); WREG32 2342 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_LINE_STIPPLE, 0); WREG32 2343 drivers/gpu/drm/radeon/r600.c WREG32(SPI_INPUT_Z, 0); WREG32 2344 drivers/gpu/drm/radeon/r600.c WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); WREG32 2345 drivers/gpu/drm/radeon/r600.c WREG32(CB_COLOR7_FRAG, 0); WREG32 2348 drivers/gpu/drm/radeon/r600.c WREG32(CB_COLOR0_BASE, 0); WREG32 2349 drivers/gpu/drm/radeon/r600.c WREG32(CB_COLOR1_BASE, 0); WREG32 2350 drivers/gpu/drm/radeon/r600.c WREG32(CB_COLOR2_BASE, 0); WREG32 2351 drivers/gpu/drm/radeon/r600.c WREG32(CB_COLOR3_BASE, 0); WREG32 2352 drivers/gpu/drm/radeon/r600.c WREG32(CB_COLOR4_BASE, 0); WREG32 2353 drivers/gpu/drm/radeon/r600.c WREG32(CB_COLOR5_BASE, 0); WREG32 2354 drivers/gpu/drm/radeon/r600.c WREG32(CB_COLOR6_BASE, 0); WREG32 2355 drivers/gpu/drm/radeon/r600.c WREG32(CB_COLOR7_BASE, 0); WREG32 2356 drivers/gpu/drm/radeon/r600.c WREG32(CB_COLOR7_FRAG, 0); WREG32 2376 drivers/gpu/drm/radeon/r600.c WREG32(TC_CNTL, tmp); WREG32 2379 drivers/gpu/drm/radeon/r600.c WREG32(HDP_HOST_PATH_CNTL, tmp); WREG32 2383 drivers/gpu/drm/radeon/r600.c WREG32(ARB_POP, tmp); WREG32 2385 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_MULTI_CHIP_CNTL, 0); WREG32 2386 drivers/gpu/drm/radeon/r600.c WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | WREG32 2388 drivers/gpu/drm/radeon/r600.c WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); WREG32 2389 drivers/gpu/drm/radeon/r600.c WREG32(VC_ENHANCE, 0); WREG32 2402 drivers/gpu/drm/radeon/r600.c WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); WREG32 2414 drivers/gpu/drm/radeon/r600.c WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); WREG32 2416 drivers/gpu/drm/radeon/r600.c WREG32(PCIE_PORT_DATA, (v)); WREG32 2428 drivers/gpu/drm/radeon/r600.c WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); WREG32 2429 drivers/gpu/drm/radeon/r600.c WREG32(SCRATCH_UMSK, 0); WREG32 2639 drivers/gpu/drm/radeon/r600.c WREG32(R600_CP_RB_WPTR, ring->wptr); WREG32 2653 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_CNTL, WREG32 2660 drivers/gpu/drm/radeon/r600.c WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); WREG32 2663 drivers/gpu/drm/radeon/r600.c WREG32(GRBM_SOFT_RESET, 0); WREG32 2665 drivers/gpu/drm/radeon/r600.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 2668 drivers/gpu/drm/radeon/r600.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 2670 drivers/gpu/drm/radeon/r600.c WREG32(CP_ME_RAM_DATA, WREG32 2674 drivers/gpu/drm/radeon/r600.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 2676 drivers/gpu/drm/radeon/r600.c WREG32(CP_PFP_UCODE_DATA, WREG32 2679 drivers/gpu/drm/radeon/r600.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 2680 drivers/gpu/drm/radeon/r600.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 2681 drivers/gpu/drm/radeon/r600.c WREG32(CP_ME_RAM_RADDR, 0); WREG32 2711 drivers/gpu/drm/radeon/r600.c WREG32(R_0086D8_CP_ME_CNTL, cp_me); WREG32 2723 drivers/gpu/drm/radeon/r600.c WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); WREG32 2726 drivers/gpu/drm/radeon/r600.c WREG32(GRBM_SOFT_RESET, 0); WREG32 2734 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_CNTL, tmp); WREG32 2735 drivers/gpu/drm/radeon/r600.c WREG32(CP_SEM_WAIT_TIMER, 0x0); WREG32 2738 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_WPTR_DELAY, 0); WREG32 2741 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); WREG32 2742 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_RPTR_WR, 0); WREG32 2744 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_WPTR, ring->wptr); WREG32 2747 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_RPTR_ADDR, WREG32 2749 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); WREG32 2750 drivers/gpu/drm/radeon/r600.c WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); WREG32 2753 drivers/gpu/drm/radeon/r600.c WREG32(SCRATCH_UMSK, 0xff); WREG32 2756 drivers/gpu/drm/radeon/r600.c WREG32(SCRATCH_UMSK, 0); WREG32 2760 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_CNTL, tmp); WREG32 2762 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_BASE, ring->gpu_addr >> 8); WREG32 2763 drivers/gpu/drm/radeon/r600.c WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); WREG32 2834 drivers/gpu/drm/radeon/r600.c WREG32(scratch, 0xCAFEDEAD); WREG32 3200 drivers/gpu/drm/radeon/r600.c WREG32(CONFIG_CNTL, temp); WREG32 3412 drivers/gpu/drm/radeon/r600.c WREG32(scratch, 0xCAFEDEAD); WREG32 3539 drivers/gpu/drm/radeon/r600.c WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); WREG32 3542 drivers/gpu/drm/radeon/r600.c WREG32(SRBM_SOFT_RESET, 0); WREG32 3546 drivers/gpu/drm/radeon/r600.c WREG32(RLC_CNTL, 0); WREG32 3551 drivers/gpu/drm/radeon/r600.c WREG32(RLC_CNTL, RLC_ENABLE); WREG32 3564 drivers/gpu/drm/radeon/r600.c WREG32(RLC_HB_CNTL, 0); WREG32 3566 drivers/gpu/drm/radeon/r600.c WREG32(RLC_HB_BASE, 0); WREG32 3567 drivers/gpu/drm/radeon/r600.c WREG32(RLC_HB_RPTR, 0); WREG32 3568 drivers/gpu/drm/radeon/r600.c WREG32(RLC_HB_WPTR, 0); WREG32 3569 drivers/gpu/drm/radeon/r600.c WREG32(RLC_HB_WPTR_LSB_ADDR, 0); WREG32 3570 drivers/gpu/drm/radeon/r600.c WREG32(RLC_HB_WPTR_MSB_ADDR, 0); WREG32 3571 drivers/gpu/drm/radeon/r600.c WREG32(RLC_MC_CNTL, 0); WREG32 3572 drivers/gpu/drm/radeon/r600.c WREG32(RLC_UCODE_CNTL, 0); WREG32 3577 drivers/gpu/drm/radeon/r600.c WREG32(RLC_UCODE_ADDR, i); WREG32 3578 drivers/gpu/drm/radeon/r600.c WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 3582 drivers/gpu/drm/radeon/r600.c WREG32(RLC_UCODE_ADDR, i); WREG32 3583 drivers/gpu/drm/radeon/r600.c WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 3586 drivers/gpu/drm/radeon/r600.c WREG32(RLC_UCODE_ADDR, 0); WREG32 3600 drivers/gpu/drm/radeon/r600.c WREG32(IH_CNTL, ih_cntl); WREG32 3601 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 3612 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 3613 drivers/gpu/drm/radeon/r600.c WREG32(IH_CNTL, ih_cntl); WREG32 3615 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_RPTR, 0); WREG32 3616 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_WPTR, 0); WREG32 3625 drivers/gpu/drm/radeon/r600.c WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); WREG32 3627 drivers/gpu/drm/radeon/r600.c WREG32(DMA_CNTL, tmp); WREG32 3628 drivers/gpu/drm/radeon/r600.c WREG32(GRBM_INT_CNTL, 0); WREG32 3629 drivers/gpu/drm/radeon/r600.c WREG32(DxMODE_INT_MASK, 0); WREG32 3630 drivers/gpu/drm/radeon/r600.c WREG32(D1GRPH_INTERRUPT_CONTROL, 0); WREG32 3631 drivers/gpu/drm/radeon/r600.c WREG32(D2GRPH_INTERRUPT_CONTROL, 0); WREG32 3633 drivers/gpu/drm/radeon/r600.c WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); WREG32 3634 drivers/gpu/drm/radeon/r600.c WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); WREG32 3636 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD1_INT_CONTROL, tmp); WREG32 3638 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD2_INT_CONTROL, tmp); WREG32 3640 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD3_INT_CONTROL, tmp); WREG32 3642 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD4_INT_CONTROL, tmp); WREG32 3645 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD5_INT_CONTROL, tmp); WREG32 3647 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD6_INT_CONTROL, tmp); WREG32 3649 drivers/gpu/drm/radeon/r600.c WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); WREG32 3651 drivers/gpu/drm/radeon/r600.c WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); WREG32 3654 drivers/gpu/drm/radeon/r600.c WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); WREG32 3656 drivers/gpu/drm/radeon/r600.c WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); WREG32 3659 drivers/gpu/drm/radeon/r600.c WREG32(DACA_AUTODETECT_INT_CONTROL, 0); WREG32 3660 drivers/gpu/drm/radeon/r600.c WREG32(DACB_AUTODETECT_INT_CONTROL, 0); WREG32 3662 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); WREG32 3664 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); WREG32 3666 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); WREG32 3668 drivers/gpu/drm/radeon/r600.c WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); WREG32 3670 drivers/gpu/drm/radeon/r600.c WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); WREG32 3700 drivers/gpu/drm/radeon/r600.c WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); WREG32 3708 drivers/gpu/drm/radeon/r600.c WREG32(INTERRUPT_CNTL, interrupt_cntl); WREG32 3710 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); WREG32 3721 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); WREG32 3722 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); WREG32 3724 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 3727 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_RPTR, 0); WREG32 3728 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_WPTR, 0); WREG32 3735 drivers/gpu/drm/radeon/r600.c WREG32(IH_CNTL, ih_cntl); WREG32 3876 drivers/gpu/drm/radeon/r600.c WREG32(CP_INT_CNTL, cp_int_cntl); WREG32 3877 drivers/gpu/drm/radeon/r600.c WREG32(DMA_CNTL, dma_cntl); WREG32 3878 drivers/gpu/drm/radeon/r600.c WREG32(DxMODE_INT_MASK, mode_int); WREG32 3879 drivers/gpu/drm/radeon/r600.c WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); WREG32 3880 drivers/gpu/drm/radeon/r600.c WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); WREG32 3881 drivers/gpu/drm/radeon/r600.c WREG32(GRBM_INT_CNTL, grbm_int_cntl); WREG32 3883 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD1_INT_CONTROL, hpd1); WREG32 3884 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD2_INT_CONTROL, hpd2); WREG32 3885 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD3_INT_CONTROL, hpd3); WREG32 3886 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD4_INT_CONTROL, hpd4); WREG32 3888 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD5_INT_CONTROL, hpd5); WREG32 3889 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD6_INT_CONTROL, hpd6); WREG32 3890 drivers/gpu/drm/radeon/r600.c WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); WREG32 3891 drivers/gpu/drm/radeon/r600.c WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); WREG32 3893 drivers/gpu/drm/radeon/r600.c WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); WREG32 3894 drivers/gpu/drm/radeon/r600.c WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); WREG32 3897 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); WREG32 3898 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); WREG32 3899 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); WREG32 3900 drivers/gpu/drm/radeon/r600.c WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); WREG32 3901 drivers/gpu/drm/radeon/r600.c WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); WREG32 3904 drivers/gpu/drm/radeon/r600.c WREG32(CG_THERMAL_INT, thermal_int); WREG32 3906 drivers/gpu/drm/radeon/r600.c WREG32(RV770_CG_THERMAL_INT, thermal_int); WREG32 3941 drivers/gpu/drm/radeon/r600.c WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); WREG32 3943 drivers/gpu/drm/radeon/r600.c WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); WREG32 3945 drivers/gpu/drm/radeon/r600.c WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); WREG32 3947 drivers/gpu/drm/radeon/r600.c WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); WREG32 3949 drivers/gpu/drm/radeon/r600.c WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); WREG32 3951 drivers/gpu/drm/radeon/r600.c WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); WREG32 3956 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD1_INT_CONTROL, tmp); WREG32 3960 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); WREG32 3967 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD2_INT_CONTROL, tmp); WREG32 3971 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); WREG32 3978 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD3_INT_CONTROL, tmp); WREG32 3982 drivers/gpu/drm/radeon/r600.c WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); WREG32 3988 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD4_INT_CONTROL, tmp); WREG32 3994 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD5_INT_CONTROL, tmp); WREG32 3999 drivers/gpu/drm/radeon/r600.c WREG32(DC_HPD6_INT_CONTROL, tmp); WREG32 4004 drivers/gpu/drm/radeon/r600.c WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); WREG32 4009 drivers/gpu/drm/radeon/r600.c WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); WREG32 4015 drivers/gpu/drm/radeon/r600.c WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); WREG32 4021 drivers/gpu/drm/radeon/r600.c WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); WREG32 4025 drivers/gpu/drm/radeon/r600.c WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); WREG32 4060 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_CNTL, tmp); WREG32 4325 drivers/gpu/drm/radeon/r600.c WREG32(IH_RB_RPTR, rptr); WREG32 4395 drivers/gpu/drm/radeon/r600.c WREG32(HDP_DEBUG1, 0); WREG32 4398 drivers/gpu/drm/radeon/r600.c WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); WREG32 4554 drivers/gpu/drm/radeon/r600.c WREG32(MM_CFGREGS_CNTL, 0x8); WREG32 4556 drivers/gpu/drm/radeon/r600.c WREG32(MM_CFGREGS_CNTL, 0); WREG32 4570 drivers/gpu/drm/radeon/r600.c WREG32(0x541c, tmp | 0x8); WREG32 4571 drivers/gpu/drm/radeon/r600.c WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); WREG32 4576 drivers/gpu/drm/radeon/r600.c WREG32(MM_CFGREGS_CNTL, 0); WREG32 4618 drivers/gpu/drm/radeon/r600.c WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); WREG32 89 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); WREG32 107 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_CNTL, rb_cntl); WREG32 127 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); WREG32 128 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); WREG32 136 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_CNTL, rb_cntl); WREG32 139 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_RPTR, 0); WREG32 140 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_WPTR, 0); WREG32 143 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_RPTR_ADDR_HI, WREG32 145 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_RPTR_ADDR_LO, WREG32 151 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); WREG32 158 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_IB_CNTL, ib_cntl); WREG32 162 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_CNTL, dma_cntl); WREG32 165 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_MODE, 1); WREG32 168 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_WPTR, ring->wptr << 2); WREG32 170 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); WREG32 251 drivers/gpu/drm/radeon/r600_dpm.c WREG32(CG_RLC_REQ_AND_RSP, 0x2); WREG32 259 drivers/gpu/drm/radeon/r600_dpm.c WREG32(CG_RLC_REQ_AND_RSP, 0x0); WREG32 261 drivers/gpu/drm/radeon/r600_dpm.c WREG32(GRBM_PWR_CNTL, 0x1); WREG32 340 drivers/gpu/drm/radeon/r600_dpm.c WREG32(CG_BSP, BSP(p) | BSU(u)); WREG32 347 drivers/gpu/drm/radeon/r600_dpm.c WREG32(CG_RT, FLS(l_to_m) | FMS(m_to_h)); WREG32 348 drivers/gpu/drm/radeon/r600_dpm.c WREG32(CG_LT, FHS(h_to_m) | FMS(m_to_l)); WREG32 354 drivers/gpu/drm/radeon/r600_dpm.c WREG32(CG_FFCT_0 + (index * 4), UTC_0(u_t) | DTC_0(d_t)); WREG32 372 drivers/gpu/drm/radeon/r600_dpm.c WREG32(CG_FTV, vrv); WREG32 524 drivers/gpu/drm/radeon/r600_dpm.c WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff); WREG32 525 drivers/gpu/drm/radeon/r600_dpm.c WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask)); WREG32 535 drivers/gpu/drm/radeon/r600_dpm.c WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff); WREG32 540 drivers/gpu/drm/radeon/r600_dpm.c WREG32(VID_UPPER_GPIO_CNTL, tmp); WREG32 550 drivers/gpu/drm/radeon/r600_dpm.c WREG32(GPIOPAD_MASK, gpio); WREG32 554 drivers/gpu/drm/radeon/r600_dpm.c WREG32(GPIOPAD_EN, gpio); WREG32 558 drivers/gpu/drm/radeon/r600_dpm.c WREG32(GPIOPAD_A, gpio); WREG32 168 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(AZ_HOT_PLUG_CONTROL, tmp); WREG32 222 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(HDMI0_AVI_INFO0 + offset, WREG32 224 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(HDMI0_AVI_INFO1 + offset, WREG32 226 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(HDMI0_AVI_INFO2 + offset, WREG32 228 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(HDMI0_AVI_INFO3 + offset, WREG32 253 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(HDMI0_AUDIO_INFO0 + offset, WREG32 255 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(HDMI0_AUDIO_INFO1 + offset, WREG32 330 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100); WREG32 331 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); WREG32 332 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ WREG32 334 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100); WREG32 335 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); WREG32 336 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ WREG32 450 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, WREG32 518 drivers/gpu/drm/radeon/r600_hdmi.c WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); WREG32 2547 drivers/gpu/drm/radeon/radeon.h WREG32(reg, tmp_); \ WREG32 257 drivers/gpu/drm/radeon/radeon_agp.c WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000); WREG32 4100 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); WREG32 4101 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); WREG32 4103 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); WREG32 4104 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); WREG32 4134 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); WREG32 4157 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); WREG32 4159 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); WREG32 4339 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); WREG32 4340 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); WREG32 4341 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); WREG32 4343 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); WREG32 4344 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); WREG32 4345 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); WREG32 4399 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); WREG32 4401 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); WREG32 4482 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); WREG32 4484 drivers/gpu/drm/radeon/radeon_atombios.c WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); WREG32 125 drivers/gpu/drm/radeon/radeon_audio.c WREG32(reg, v); WREG32 267 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); WREG32 270 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D1VGA_CONTROL, WREG32 273 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D2VGA_CONTROL, WREG32 276 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_VGA_RENDER_CONTROL, WREG32 279 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); WREG32 284 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_BUS_CNTL, bus_cntl); WREG32 286 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); WREG32 287 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); WREG32 288 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); WREG32 290 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_ROM_CNTL, rom_cntl); WREG32 314 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); WREG32 316 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); WREG32 318 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D1VGA_CONTROL, WREG32 321 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D2VGA_CONTROL, WREG32 324 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_VGA_RENDER_CONTROL, WREG32 331 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | WREG32 339 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); WREG32 341 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); WREG32 347 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); WREG32 354 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_VIPH_CONTROL, viph_control); WREG32 355 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_BUS_CNTL, bus_cntl); WREG32 356 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); WREG32 357 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); WREG32 358 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); WREG32 359 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_ROM_CNTL, rom_cntl); WREG32 393 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); WREG32 395 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); WREG32 397 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D1VGA_CONTROL, WREG32 400 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D2VGA_CONTROL, WREG32 403 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_VGA_RENDER_CONTROL, WREG32 406 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_ROM_CNTL, WREG32 411 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); WREG32 412 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, WREG32 414 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, WREG32 416 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, WREG32 418 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, WREG32 420 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); WREG32 425 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_VIPH_CONTROL, viph_control); WREG32 426 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_BUS_CNTL, bus_cntl); WREG32 427 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); WREG32 428 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); WREG32 429 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); WREG32 430 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_ROM_CNTL, rom_cntl); WREG32 431 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); WREG32 432 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); WREG32 433 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); WREG32 434 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); WREG32 435 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); WREG32 436 drivers/gpu/drm/radeon/radeon_bios.c WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); WREG32 463 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_SEPROM_CNTL1, WREG32 466 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_GPIOPAD_A, 0); WREG32 467 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_GPIOPAD_EN, 0); WREG32 468 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_GPIOPAD_MASK, 0); WREG32 471 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); WREG32 474 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); WREG32 477 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D1VGA_CONTROL, WREG32 480 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D2VGA_CONTROL, WREG32 483 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_VGA_RENDER_CONTROL, WREG32 489 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); WREG32 490 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_VIPH_CONTROL, viph_control); WREG32 491 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RV370_BUS_CNTL, bus_cntl); WREG32 492 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); WREG32 493 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); WREG32 494 drivers/gpu/drm/radeon/radeon_bios.c WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); WREG32 495 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_GPIOPAD_A, gpiopad_a); WREG32 496 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_GPIOPAD_EN, gpiopad_en); WREG32 497 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); WREG32 531 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_SEPROM_CNTL1, WREG32 536 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); WREG32 540 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); WREG32 542 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); WREG32 545 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_CRTC_GEN_CNTL, WREG32 550 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_CRTC2_GEN_CNTL, WREG32 555 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_CRTC_EXT_CNTL, WREG32 561 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); WREG32 567 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); WREG32 568 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_VIPH_CONTROL, viph_control); WREG32 570 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RV370_BUS_CNTL, bus_cntl); WREG32 572 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_BUS_CNTL, bus_cntl); WREG32 573 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); WREG32 575 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32 577 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); WREG32 579 drivers/gpu/drm/radeon/radeon_bios.c WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); WREG32 2914 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); WREG32 2924 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); WREG32 2968 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); WREG32 2978 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); WREG32 3031 drivers/gpu/drm/radeon/radeon_combios.c WREG32(addr, val); WREG32 3036 drivers/gpu/drm/radeon/radeon_combios.c WREG32(addr, val); WREG32 3046 drivers/gpu/drm/radeon/radeon_combios.c WREG32(addr, tmp); WREG32 3056 drivers/gpu/drm/radeon/radeon_combios.c WREG32(addr, tmp); WREG32 3218 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); WREG32 3224 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); WREG32 3245 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_MEM_CNTL, mem_cntl); WREG32 3284 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_MEM_CNTL, mem_cntl); WREG32 3322 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_CONFIG_MEMSIZE, mem_size); WREG32 3436 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); WREG32 3437 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); WREG32 3438 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); WREG32 3454 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); WREG32 3556 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); WREG32 3557 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); WREG32 3592 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); WREG32 3627 drivers/gpu/drm/radeon/radeon_combios.c WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); WREG32 44 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); WREG32 51 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); WREG32 58 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); WREG32 99 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, WREG32 101 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, WREG32 103 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); WREG32 104 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | WREG32 110 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, WREG32 113 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, WREG32 117 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, WREG32 119 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); WREG32 120 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | WREG32 124 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, WREG32 129 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); WREG32 132 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); WREG32 218 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); WREG32 219 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); WREG32 220 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, WREG32 223 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); WREG32 224 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); WREG32 225 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, WREG32 234 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset, WREG32 238 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, WREG32 243 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, WREG32 223 drivers/gpu/drm/radeon/radeon_device.c WREG32(reg, tmp); WREG32 252 drivers/gpu/drm/radeon/radeon_device.c WREG32(RADEON_SURFACE_CNTL, 0); WREG32 908 drivers/gpu/drm/radeon/radeon_device.c WREG32(reg*4, val); WREG32 57 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); WREG32 59 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); WREG32 60 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); WREG32 61 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); WREG32 63 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); WREG32 64 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); WREG32 65 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); WREG32 67 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); WREG32 68 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUT_RW_MODE, 0); WREG32 69 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); WREG32 76 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUT_30_COLOR, WREG32 95 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); WREG32 97 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); WREG32 98 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); WREG32 99 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); WREG32 101 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); WREG32 102 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); WREG32 103 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); WREG32 105 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); WREG32 106 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); WREG32 108 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); WREG32 113 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, WREG32 132 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, WREG32 135 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, WREG32 137 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, WREG32 139 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, WREG32 143 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); WREG32 145 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); WREG32 146 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); WREG32 147 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); WREG32 149 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); WREG32 150 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); WREG32 151 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); WREG32 153 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); WREG32 154 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); WREG32 156 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); WREG32 161 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, WREG32 167 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, WREG32 172 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, WREG32 175 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, WREG32 178 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, WREG32 182 drivers/gpu/drm/radeon/radeon_display.c WREG32(0x6940 + radeon_crtc->crtc_offset, 0); WREG32 187 drivers/gpu/drm/radeon/radeon_display.c WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, WREG32 206 drivers/gpu/drm/radeon/radeon_display.c WREG32(RADEON_DAC_CNTL2, dac2_cntl); WREG32 213 drivers/gpu/drm/radeon/radeon_display.c WREG32(RADEON_PALETTE_30_DATA, WREG32 101 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(chan->rec.mask_clk_reg, tmp); WREG32 110 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_CONTROL + aux_offset[instance], tmp); WREG32 113 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_CONTROL + aux_offset[instance], WREG32 115 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_CONTROL + aux_offset[instance], WREG32 121 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_DATA + aux_offset[instance], WREG32 125 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_DATA + aux_offset[instance], WREG32 129 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_DATA + aux_offset[instance], WREG32 133 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_DATA + aux_offset[instance], WREG32 139 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_DATA + aux_offset[instance], WREG32 145 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); WREG32 148 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_CONTROL + aux_offset[instance], WREG32 179 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_DATA + aux_offset[instance], WREG32 194 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); WREG32 51 drivers/gpu/drm/radeon/radeon_dp_mst.c WREG32(NI_DIG_BE_CNTL + primary->offset, reg); WREG32 90 drivers/gpu/drm/radeon/radeon_dp_mst.c WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp); WREG32 92 drivers/gpu/drm/radeon/radeon_dp_mst.c WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1); WREG32 177 drivers/gpu/drm/radeon/radeon_dp_mst.c WREG32(NI_DP_MSE_RATE_CNTL + offset, val); WREG32 76 drivers/gpu/drm/radeon/radeon_fence.c WREG32(drv->scratch_reg, seq); WREG32 120 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | WREG32 123 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | WREG32 134 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_clk_reg, temp); WREG32 139 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->a_clk_reg, temp); WREG32 142 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->a_data_reg, temp); WREG32 146 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->en_clk_reg, temp); WREG32 149 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->en_data_reg, temp); WREG32 153 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_clk_reg, temp); WREG32 157 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_data_reg, temp); WREG32 172 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_clk_reg, temp); WREG32 176 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_data_reg, temp); WREG32 221 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->en_clk_reg, val); WREG32 234 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->en_data_reg, val); WREG32 355 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); WREG32 469 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, (RADEON_I2C_DONE | WREG32 473 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_data, (p->addr << 1) & 0xff); WREG32 474 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_data, 0); WREG32 475 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | WREG32 479 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, reg); WREG32 490 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); WREG32 502 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, (RADEON_I2C_DONE | WREG32 506 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); WREG32 507 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | WREG32 511 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); WREG32 522 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); WREG32 529 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, (RADEON_I2C_DONE | WREG32 533 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_data, (p->addr << 1) & 0xff); WREG32 534 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_data, p->buf[j]); WREG32 535 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | WREG32 539 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, reg); WREG32 550 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); WREG32 560 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, 0); WREG32 561 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_1, 0); WREG32 562 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, (RADEON_I2C_DONE | WREG32 570 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(RADEON_BIOS_6_SCRATCH, tmp); WREG32 603 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_clk_reg, tmp); WREG32 608 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->mask_data_reg, tmp); WREG32 614 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->a_clk_reg, tmp); WREG32 619 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->a_data_reg, tmp); WREG32 625 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->en_clk_reg, tmp); WREG32 630 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(rec->en_data_reg, tmp); WREG32 635 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); WREG32 638 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(0x494, saved2 | 0x1); WREG32 640 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); WREG32 672 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | WREG32 675 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); WREG32 677 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, 0); WREG32 679 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); WREG32 680 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_DATA, 0); WREG32 682 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); WREG32 683 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | WREG32 686 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL1, reg); WREG32 687 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); WREG32 698 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); WREG32 716 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | WREG32 719 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); WREG32 721 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, 0); WREG32 723 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); WREG32 724 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); WREG32 725 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | WREG32 728 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); WREG32 729 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); WREG32 740 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); WREG32 756 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | WREG32 759 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); WREG32 761 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, 0); WREG32 763 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); WREG32 765 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); WREG32 767 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); WREG32 768 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | WREG32 771 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL1, reg); WREG32 772 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); WREG32 783 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); WREG32 795 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | WREG32 798 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); WREG32 800 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_RESET, 0); WREG32 802 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); WREG32 803 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL1, saved1); WREG32 804 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(0x494, saved2); WREG32 807 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(RADEON_BIOS_6_SCRATCH, tmp); WREG32 580 drivers/gpu/drm/radeon/radeon_irq_kms.c WREG32(reg, tmp |= mask); WREG32 583 drivers/gpu/drm/radeon/radeon_irq_kms.c WREG32(reg, tmp & ~mask); WREG32 44 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); WREG32 45 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); WREG32 46 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); WREG32 203 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); WREG32 204 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); WREG32 205 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); WREG32 206 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); WREG32 207 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); WREG32 208 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); WREG32 209 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); WREG32 210 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); WREG32 542 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(gen_cntl_reg, gen_cntl_val); WREG32 546 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); WREG32 550 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); WREG32 552 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); WREG32 554 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); WREG32 555 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); WREG32 556 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); WREG32 678 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); WREG32 679 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32 681 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); WREG32 682 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); WREG32 715 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); WREG32 716 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); WREG32 717 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); WREG32 725 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); WREG32 726 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); WREG32 727 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); WREG32 728 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); WREG32 94 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); WREG32 97 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); WREG32 102 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); WREG32 112 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); WREG32 122 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); WREG32 125 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); WREG32 129 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); WREG32 240 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); WREG32 241 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); WREG32 242 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); WREG32 245 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CLOCK_CNTL_INDEX, 0); WREG32 550 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); WREG32 551 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL, dac_cntl); WREG32 552 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); WREG32 600 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); WREG32 603 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL2, dac2_cntl); WREG32 610 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); WREG32 613 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL2, dac2_cntl); WREG32 633 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); WREG32 671 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC_EXT_CNTL, tmp); WREG32 688 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_EXT_CNTL, tmp); WREG32 692 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL, tmp); WREG32 699 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_MACRO_CNTL, tmp); WREG32 707 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL, dac_cntl); WREG32 708 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); WREG32 709 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); WREG32 710 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); WREG32 749 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); WREG32 871 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); WREG32 872 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); WREG32 873 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); WREG32 915 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); WREG32 1007 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); WREG32 1112 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); WREG32 1115 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); WREG32 1118 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32 1119 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); WREG32 1210 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); WREG32 1229 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL, dac_cntl); WREG32 1257 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL2, dac2_cntl); WREG32 1282 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL2, dac2_cntl); WREG32 1287 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); WREG32 1289 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); WREG32 1291 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); WREG32 1294 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); WREG32 1325 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); WREG32 1327 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_GEN_CNTL, WREG32 1332 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); WREG32 1334 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_EXT_CNTL, WREG32 1340 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_DAC_CNTL, WREG32 1348 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_DAC_CNTL, WREG32 1368 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); WREG32 1369 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); WREG32 1370 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32 1371 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); WREG32 1372 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL2, dac_cntl2); WREG32 1396 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL2, tmp); WREG32 1405 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_MASTER_CNTL, tmp); WREG32 1415 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_DAC_CNTL, tmp); WREG32 1422 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); WREG32 1434 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); WREG32 1435 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); WREG32 1436 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); WREG32 1437 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL2, dac_cntl2); WREG32 1472 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_GPIO_MONID, tmp); WREG32 1474 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON | WREG32 1480 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX | WREG32 1483 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | WREG32 1486 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); WREG32 1487 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); WREG32 1488 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000); WREG32 1489 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0); WREG32 1490 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000); WREG32 1491 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0); WREG32 1493 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008); WREG32 1494 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800); WREG32 1495 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001); WREG32 1496 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080); WREG32 1513 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a); WREG32 1514 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b); WREG32 1515 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c); WREG32 1516 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d); WREG32 1517 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e); WREG32 1518 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f); WREG32 1519 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp); WREG32 1520 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp); WREG32 1521 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid); WREG32 1522 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid); WREG32 1523 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32 1524 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); WREG32 1525 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); WREG32 1526 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_GPIO_MONID, gpio_monid); WREG32 1606 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC_EXT_CNTL, tmp); WREG32 1611 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_GEN_CNTL, tmp); WREG32 1617 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); WREG32 1620 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_HW_DEBUG, tmp); WREG32 1629 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_DAC_CNTL, tmp); WREG32 1644 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_EXT_CNTL, tmp); WREG32 1647 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL2, tmp); WREG32 1660 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_CNTL2, dac_cntl2); WREG32 1661 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); WREG32 1662 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); WREG32 1665 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); WREG32 1667 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32 1669 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); WREG32 1672 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); WREG32 285 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); WREG32 297 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); WREG32 309 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HOST_WRITE_DATA, value); WREG32 311 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); WREG32 312 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); WREG32 320 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); WREG32 331 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); WREG32 332 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); WREG32 340 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); WREG32 396 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); WREG32 419 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); WREG32 420 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); WREG32 421 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); WREG32 751 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | WREG32 760 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_DAC_CNTL, tmp); WREG32 781 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl); WREG32 782 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1); WREG32 783 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1); WREG32 784 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_HSTART, const_ptr->hor_start); WREG32 786 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1); WREG32 787 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1); WREG32 788 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_FTOTAL, tv_ftotal); WREG32 789 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1); WREG32 790 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2); WREG32 792 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl); WREG32 793 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl); WREG32 794 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl); WREG32 796 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | WREG32 805 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST)); WREG32 808 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE)); WREG32 809 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); WREG32 810 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1); WREG32 811 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2); WREG32 812 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN | WREG32 817 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_CRC_CNTL, 0); WREG32 819 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); WREG32 821 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | WREG32 823 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) | WREG32 826 drivers/gpu/drm/radeon/radeon_legacy_tv.c WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); WREG32 979 drivers/gpu/drm/radeon/radeon_ttm.c WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); WREG32 981 drivers/gpu/drm/radeon/radeon_ttm.c WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); WREG32 151 drivers/gpu/drm/radeon/rs400.c WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); WREG32 152 drivers/gpu/drm/radeon/rs400.c WREG32(RS480_AGP_BASE_2, 0); WREG32 159 drivers/gpu/drm/radeon/rs400.c WREG32(RADEON_BUS_CNTL, tmp); WREG32 161 drivers/gpu/drm/radeon/rs400.c WREG32(RADEON_MC_AGP_LOCATION, tmp); WREG32 163 drivers/gpu/drm/radeon/rs400.c WREG32(RADEON_BUS_CNTL, tmp); WREG32 291 drivers/gpu/drm/radeon/rs400.c WREG32(RS480_NB_MC_INDEX, reg & 0xff); WREG32 293 drivers/gpu/drm/radeon/rs400.c WREG32(RS480_NB_MC_INDEX, 0xff); WREG32 303 drivers/gpu/drm/radeon/rs400.c WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); WREG32 304 drivers/gpu/drm/radeon/rs400.c WREG32(RS480_NB_MC_DATA, (v)); WREG32 305 drivers/gpu/drm/radeon/rs400.c WREG32(RS480_NB_MC_INDEX, 0xff); WREG32 403 drivers/gpu/drm/radeon/rs400.c WREG32(R_000148_MC_FB_LOCATION, WREG32 126 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); WREG32 129 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, WREG32 131 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, WREG32 133 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, WREG32 146 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); WREG32 206 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); WREG32 209 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); WREG32 212 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); WREG32 215 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); WREG32 237 drivers/gpu/drm/radeon/rs600.c WREG32(voltage->gpio.reg, tmp); WREG32 246 drivers/gpu/drm/radeon/rs600.c WREG32(voltage->gpio.reg, tmp); WREG32 329 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); WREG32 347 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); WREG32 388 drivers/gpu/drm/radeon/rs600.c WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); WREG32 396 drivers/gpu/drm/radeon/rs600.c WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); WREG32 413 drivers/gpu/drm/radeon/rs600.c WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, WREG32 417 drivers/gpu/drm/radeon/rs600.c WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, WREG32 440 drivers/gpu/drm/radeon/rs600.c WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, WREG32 444 drivers/gpu/drm/radeon/rs600.c WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, WREG32 471 drivers/gpu/drm/radeon/rs600.c WREG32(RADEON_CP_CSQ_CNTL, 0); WREG32 473 drivers/gpu/drm/radeon/rs600.c WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); WREG32 474 drivers/gpu/drm/radeon/rs600.c WREG32(RADEON_CP_RB_RPTR_WR, 0); WREG32 475 drivers/gpu/drm/radeon/rs600.c WREG32(RADEON_CP_RB_WPTR, 0); WREG32 476 drivers/gpu/drm/radeon/rs600.c WREG32(RADEON_CP_RB_CNTL, tmp); WREG32 482 drivers/gpu/drm/radeon/rs600.c WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | WREG32 486 drivers/gpu/drm/radeon/rs600.c WREG32(R_0000F0_RBBM_SOFT_RESET, 0); WREG32 491 drivers/gpu/drm/radeon/rs600.c WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); WREG32 494 drivers/gpu/drm/radeon/rs600.c WREG32(R_0000F0_RBBM_SOFT_RESET, 0); WREG32 499 drivers/gpu/drm/radeon/rs600.c WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); WREG32 502 drivers/gpu/drm/radeon/rs600.c WREG32(R_0000F0_RBBM_SOFT_RESET, 0); WREG32 570 drivers/gpu/drm/radeon/rs600.c WREG32(RADEON_BUS_CNTL, tmp); WREG32 677 drivers/gpu/drm/radeon/rs600.c WREG32(R_000040_GEN_INT_CNTL, 0); WREG32 700 drivers/gpu/drm/radeon/rs600.c WREG32(R_000040_GEN_INT_CNTL, tmp); WREG32 701 drivers/gpu/drm/radeon/rs600.c WREG32(R_006540_DxMODE_INT_MASK, mode_int); WREG32 702 drivers/gpu/drm/radeon/rs600.c WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); WREG32 703 drivers/gpu/drm/radeon/rs600.c WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); WREG32 705 drivers/gpu/drm/radeon/rs600.c WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); WREG32 722 drivers/gpu/drm/radeon/rs600.c WREG32(R_006534_D1MODE_VBLANK_STATUS, WREG32 726 drivers/gpu/drm/radeon/rs600.c WREG32(R_006D34_D2MODE_VBLANK_STATUS, WREG32 732 drivers/gpu/drm/radeon/rs600.c WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); WREG32 737 drivers/gpu/drm/radeon/rs600.c WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); WREG32 749 drivers/gpu/drm/radeon/rs600.c WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); WREG32 755 drivers/gpu/drm/radeon/rs600.c WREG32(R_000044_GEN_INT_STATUS, irqs); WREG32 764 drivers/gpu/drm/radeon/rs600.c WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); WREG32 765 drivers/gpu/drm/radeon/rs600.c WREG32(R_000040_GEN_INT_CNTL, 0); WREG32 766 drivers/gpu/drm/radeon/rs600.c WREG32(R_006540_DxMODE_INT_MASK, 0); WREG32 834 drivers/gpu/drm/radeon/rs600.c WREG32(RADEON_BUS_CNTL, msi_rearm); WREG32 835 drivers/gpu/drm/radeon/rs600.c WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); WREG32 838 drivers/gpu/drm/radeon/rs600.c WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); WREG32 917 drivers/gpu/drm/radeon/rs600.c WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); WREG32 918 drivers/gpu/drm/radeon/rs600.c WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); WREG32 919 drivers/gpu/drm/radeon/rs600.c WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); WREG32 920 drivers/gpu/drm/radeon/rs600.c WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); WREG32 930 drivers/gpu/drm/radeon/rs600.c WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | WREG32 942 drivers/gpu/drm/radeon/rs600.c WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | WREG32 944 drivers/gpu/drm/radeon/rs600.c WREG32(R_000074_MC_IND_DATA, v); WREG32 979 drivers/gpu/drm/radeon/rs600.c WREG32(R_000134_HDP_FB_LOCATION, WREG32 249 drivers/gpu/drm/radeon/rs690.c WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); WREG32 622 drivers/gpu/drm/radeon/rs690.c WREG32(R_006C9C_DCP_CONTROL, 0); WREG32 624 drivers/gpu/drm/radeon/rs690.c WREG32(R_006C9C_DCP_CONTROL, 2); WREG32 634 drivers/gpu/drm/radeon/rs690.c WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); WREG32 645 drivers/gpu/drm/radeon/rs690.c WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); WREG32 646 drivers/gpu/drm/radeon/rs690.c WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); WREG32 647 drivers/gpu/drm/radeon/rs690.c WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); WREG32 648 drivers/gpu/drm/radeon/rs690.c WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); WREG32 657 drivers/gpu/drm/radeon/rs690.c WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); WREG32 659 drivers/gpu/drm/radeon/rs690.c WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); WREG32 669 drivers/gpu/drm/radeon/rs690.c WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | WREG32 671 drivers/gpu/drm/radeon/rs690.c WREG32(R_00007C_MC_DATA, v); WREG32 672 drivers/gpu/drm/radeon/rs690.c WREG32(R_000078_MC_INDEX, 0x7F); WREG32 690 drivers/gpu/drm/radeon/rs690.c WREG32(R_000134_HDP_FB_LOCATION, WREG32 280 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_PWM_CTRL_REG1, WREG32 284 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT); WREG32 285 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT); WREG32 286 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT); WREG32 287 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT); WREG32 293 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2, WREG32 297 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3, WREG32 300 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4, WREG32 325 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT); WREG32 326 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT); WREG32 327 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT); WREG32 328 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT); WREG32 329 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT); WREG32 331 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT); WREG32 332 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT); WREG32 333 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT); WREG32 334 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT); WREG32 335 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT); WREG32 356 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT); WREG32 357 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT); WREG32 358 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT); WREG32 359 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT); WREG32 368 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate); WREG32 369 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate); WREG32 370 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate); WREG32 371 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate); WREG32 372 drivers/gpu/drm/radeon/rs780_dpm.c WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate); WREG32 153 drivers/gpu/drm/radeon/rv515.c WREG32(R_000300_VGA_RENDER_CONTROL, WREG32 218 drivers/gpu/drm/radeon/rv515.c WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); WREG32 220 drivers/gpu/drm/radeon/rv515.c WREG32(MC_IND_INDEX, 0); WREG32 231 drivers/gpu/drm/radeon/rv515.c WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); WREG32 232 drivers/gpu/drm/radeon/rv515.c WREG32(MC_IND_DATA, (v)); WREG32 233 drivers/gpu/drm/radeon/rv515.c WREG32(MC_IND_INDEX, 0); WREG32 307 drivers/gpu/drm/radeon/rv515.c WREG32(R_000300_VGA_RENDER_CONTROL, 0); WREG32 316 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 318 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); WREG32 319 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 330 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32 333 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); WREG32 334 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); WREG32 351 drivers/gpu/drm/radeon/rv515.c WREG32(R600_BIF_FB_EN, 0); WREG32 355 drivers/gpu/drm/radeon/rv515.c WREG32(R700_MC_CITF_CNTL, blackout); WREG32 357 drivers/gpu/drm/radeon/rv515.c WREG32(R600_CITF_CNTL, blackout); WREG32 369 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); WREG32 374 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); WREG32 389 drivers/gpu/drm/radeon/rv515.c WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, WREG32 391 drivers/gpu/drm/radeon/rv515.c WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, WREG32 394 drivers/gpu/drm/radeon/rv515.c WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, WREG32 396 drivers/gpu/drm/radeon/rv515.c WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, WREG32 400 drivers/gpu/drm/radeon/rv515.c WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], WREG32 402 drivers/gpu/drm/radeon/rv515.c WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], WREG32 405 drivers/gpu/drm/radeon/rv515.c WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); WREG32 414 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); WREG32 419 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); WREG32 424 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); WREG32 443 drivers/gpu/drm/radeon/rv515.c WREG32(R700_MC_CITF_CNTL, tmp); WREG32 445 drivers/gpu/drm/radeon/rv515.c WREG32(R600_CITF_CNTL, tmp); WREG32 447 drivers/gpu/drm/radeon/rv515.c WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); WREG32 454 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); WREG32 465 drivers/gpu/drm/radeon/rv515.c WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); WREG32 467 drivers/gpu/drm/radeon/rv515.c WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); WREG32 481 drivers/gpu/drm/radeon/rv515.c WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); WREG32 486 drivers/gpu/drm/radeon/rv515.c WREG32(R_000134_HDP_FB_LOCATION, WREG32 717 drivers/gpu/drm/radeon/rv515.c WREG32(0x659C + crtc->crtc_offset, 0x0); WREG32 718 drivers/gpu/drm/radeon/rv515.c WREG32(0x6594 + crtc->crtc_offset, 0x705); WREG32 719 drivers/gpu/drm/radeon/rv515.c WREG32(0x65A4 + crtc->crtc_offset, 0x10001); WREG32 720 drivers/gpu/drm/radeon/rv515.c WREG32(0x65D8 + crtc->crtc_offset, 0x0); WREG32 721 drivers/gpu/drm/radeon/rv515.c WREG32(0x65B0 + crtc->crtc_offset, 0x0); WREG32 722 drivers/gpu/drm/radeon/rv515.c WREG32(0x65C0 + crtc->crtc_offset, 0x0); WREG32 723 drivers/gpu/drm/radeon/rv515.c WREG32(0x65D4 + crtc->crtc_offset, 0x0); WREG32 724 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x0); WREG32 725 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x841880A8); WREG32 726 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x1); WREG32 727 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x84208680); WREG32 728 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x2); WREG32 729 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFF880B0); WREG32 730 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x100); WREG32 731 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x83D88088); WREG32 732 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x101); WREG32 733 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x84608680); WREG32 734 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x102); WREG32 735 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFF080D0); WREG32 736 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x200); WREG32 737 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x83988068); WREG32 738 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x201); WREG32 739 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x84A08680); WREG32 740 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x202); WREG32 741 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFF080F8); WREG32 742 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x300); WREG32 743 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x83588058); WREG32 744 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x301); WREG32 745 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x84E08660); WREG32 746 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x302); WREG32 747 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFF88120); WREG32 748 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x400); WREG32 749 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x83188040); WREG32 750 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x401); WREG32 751 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x85008660); WREG32 752 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x402); WREG32 753 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFF88150); WREG32 754 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x500); WREG32 755 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x82D88030); WREG32 756 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x501); WREG32 757 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x85408640); WREG32 758 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x502); WREG32 759 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFF88180); WREG32 760 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x600); WREG32 761 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x82A08018); WREG32 762 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x601); WREG32 763 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x85808620); WREG32 764 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x602); WREG32 765 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFF081B8); WREG32 766 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x700); WREG32 767 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x82608010); WREG32 768 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x701); WREG32 769 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x85A08600); WREG32 770 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x702); WREG32 771 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x800081F0); WREG32 772 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x800); WREG32 773 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8228BFF8); WREG32 774 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x801); WREG32 775 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x85E085E0); WREG32 776 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x802); WREG32 777 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFF88228); WREG32 778 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10000); WREG32 779 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x82A8BF00); WREG32 780 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10001); WREG32 781 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x82A08CC0); WREG32 782 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10002); WREG32 783 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8008BEF8); WREG32 784 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10100); WREG32 785 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x81F0BF28); WREG32 786 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10101); WREG32 787 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x83608CA0); WREG32 788 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10102); WREG32 789 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8018BED0); WREG32 790 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10200); WREG32 791 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8148BF38); WREG32 792 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10201); WREG32 793 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x84408C80); WREG32 794 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10202); WREG32 795 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8008BEB8); WREG32 796 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10300); WREG32 797 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80B0BF78); WREG32 798 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10301); WREG32 799 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x85008C20); WREG32 800 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10302); WREG32 801 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8020BEA0); WREG32 802 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10400); WREG32 803 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8028BF90); WREG32 804 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10401); WREG32 805 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x85E08BC0); WREG32 806 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10402); WREG32 807 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8018BE90); WREG32 808 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10500); WREG32 809 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFB8BFB0); WREG32 810 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10501); WREG32 811 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x86C08B40); WREG32 812 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10502); WREG32 813 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8010BE90); WREG32 814 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10600); WREG32 815 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBF58BFC8); WREG32 816 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10601); WREG32 817 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x87A08AA0); WREG32 818 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10602); WREG32 819 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8010BE98); WREG32 820 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10700); WREG32 821 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBF10BFF0); WREG32 822 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10701); WREG32 823 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x886089E0); WREG32 824 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10702); WREG32 825 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8018BEB0); WREG32 826 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10800); WREG32 827 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBED8BFE8); WREG32 828 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10801); WREG32 829 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x89408940); WREG32 830 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x10802); WREG32 831 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFE8BED8); WREG32 832 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20000); WREG32 833 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008000); WREG32 834 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20001); WREG32 835 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x90008000); WREG32 836 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20002); WREG32 837 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008000); WREG32 838 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20003); WREG32 839 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008000); WREG32 840 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20100); WREG32 841 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80108000); WREG32 842 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20101); WREG32 843 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8FE0BF70); WREG32 844 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20102); WREG32 845 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFE880C0); WREG32 846 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20103); WREG32 847 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008000); WREG32 848 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20200); WREG32 849 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8018BFF8); WREG32 850 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20201); WREG32 851 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8F80BF08); WREG32 852 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20202); WREG32 853 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFD081A0); WREG32 854 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20203); WREG32 855 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFF88000); WREG32 856 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20300); WREG32 857 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80188000); WREG32 858 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20301); WREG32 859 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8EE0BEC0); WREG32 860 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20302); WREG32 861 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFB082A0); WREG32 862 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20303); WREG32 863 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008000); WREG32 864 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20400); WREG32 865 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80188000); WREG32 866 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20401); WREG32 867 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8E00BEA0); WREG32 868 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20402); WREG32 869 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBF8883C0); WREG32 870 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20403); WREG32 871 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008000); WREG32 872 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20500); WREG32 873 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80188000); WREG32 874 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20501); WREG32 875 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8D00BE90); WREG32 876 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20502); WREG32 877 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBF588500); WREG32 878 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20503); WREG32 879 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008008); WREG32 880 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20600); WREG32 881 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80188000); WREG32 882 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20601); WREG32 883 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8BC0BE98); WREG32 884 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20602); WREG32 885 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBF308660); WREG32 886 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20603); WREG32 887 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008008); WREG32 888 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20700); WREG32 889 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80108000); WREG32 890 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20701); WREG32 891 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8A80BEB0); WREG32 892 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20702); WREG32 893 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBF0087C0); WREG32 894 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20703); WREG32 895 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008008); WREG32 896 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20800); WREG32 897 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80108000); WREG32 898 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20801); WREG32 899 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8920BED0); WREG32 900 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20802); WREG32 901 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBED08920); WREG32 902 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x20803); WREG32 903 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008010); WREG32 904 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30000); WREG32 905 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x90008000); WREG32 906 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30001); WREG32 907 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x80008000); WREG32 908 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30100); WREG32 909 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8FE0BF90); WREG32 910 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30101); WREG32 911 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFF880A0); WREG32 912 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30200); WREG32 913 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8F60BF40); WREG32 914 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30201); WREG32 915 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFE88180); WREG32 916 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30300); WREG32 917 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8EC0BF00); WREG32 918 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30301); WREG32 919 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFC88280); WREG32 920 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30400); WREG32 921 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8DE0BEE0); WREG32 922 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30401); WREG32 923 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBFA083A0); WREG32 924 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30500); WREG32 925 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8CE0BED0); WREG32 926 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30501); WREG32 927 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBF7884E0); WREG32 928 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30600); WREG32 929 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8BA0BED8); WREG32 930 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30601); WREG32 931 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBF508640); WREG32 932 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30700); WREG32 933 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8A60BEE8); WREG32 934 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30701); WREG32 935 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBF2087A0); WREG32 936 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30800); WREG32 937 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0x8900BF00); WREG32 938 drivers/gpu/drm/radeon/rv515.c WREG32(index_reg, 0x30801); WREG32 939 drivers/gpu/drm/radeon/rv515.c WREG32(data_reg, 0xBF008900); WREG32 1259 drivers/gpu/drm/radeon/rv515.c WREG32(LB_MAX_REQ_OUTSTANDING, tmp); WREG32 1270 drivers/gpu/drm/radeon/rv515.c WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); WREG32 1271 drivers/gpu/drm/radeon/rv515.c WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); WREG32 1272 drivers/gpu/drm/radeon/rv515.c WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); WREG32 1273 drivers/gpu/drm/radeon/rv515.c WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); WREG32 814 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32(SQM_RATIO, sqm_ratio); WREG32 825 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32(ARB_RFSH_RATE, arb_refresh_rate); WREG32 989 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32 1195 drivers/gpu/drm/radeon/rv6xx_dpm.c WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32 408 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate); WREG32 421 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC_ARB_DRAM_TIMING_3, dram_timing); WREG32 422 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2); WREG32 431 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC_ARB_DRAM_TIMING_2, dram_timing); WREG32 432 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2); WREG32 441 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC_ARB_DRAM_TIMING_1, dram_timing); WREG32 442 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2); WREG32 445 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC_ARB_DRAM_TIMING, old_dram_timing); WREG32 446 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2); WREG32 484 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl); WREG32 485 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC4_IO_DQ_PAD_CNTL_D0_I1, mc4_io_pad_cntl); WREG32 490 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC4_IO_QS_PAD_CNTL_D0_I0, mc4_io_pad_cntl); WREG32 491 drivers/gpu/drm/radeon/rv730_dpm.c WREG32(MC4_IO_QS_PAD_CNTL_D0_I1, mc4_io_pad_cntl); WREG32 816 drivers/gpu/drm/radeon/rv770.c WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); WREG32 819 drivers/gpu/drm/radeon/rv770.c WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, WREG32 822 drivers/gpu/drm/radeon/rv770.c WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); WREG32 823 drivers/gpu/drm/radeon/rv770.c WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); WREG32 825 drivers/gpu/drm/radeon/rv770.c WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); WREG32 826 drivers/gpu/drm/radeon/rv770.c WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); WREG32 828 drivers/gpu/drm/radeon/rv770.c WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, WREG32 830 drivers/gpu/drm/radeon/rv770.c WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, WREG32 843 drivers/gpu/drm/radeon/rv770.c WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); WREG32 910 drivers/gpu/drm/radeon/rv770.c WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | WREG32 913 drivers/gpu/drm/radeon/rv770.c WREG32(VM_L2_CNTL2, 0); WREG32 914 drivers/gpu/drm/radeon/rv770.c WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); WREG32 920 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); WREG32 921 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); WREG32 922 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); WREG32 924 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); WREG32 925 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); WREG32 926 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); WREG32 927 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); WREG32 928 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); WREG32 929 drivers/gpu/drm/radeon/rv770.c WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); WREG32 930 drivers/gpu/drm/radeon/rv770.c WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); WREG32 931 drivers/gpu/drm/radeon/rv770.c WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); WREG32 932 drivers/gpu/drm/radeon/rv770.c WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | WREG32 934 drivers/gpu/drm/radeon/rv770.c WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 937 drivers/gpu/drm/radeon/rv770.c WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); WREG32 954 drivers/gpu/drm/radeon/rv770.c WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); WREG32 957 drivers/gpu/drm/radeon/rv770.c WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | WREG32 959 drivers/gpu/drm/radeon/rv770.c WREG32(VM_L2_CNTL2, 0); WREG32 960 drivers/gpu/drm/radeon/rv770.c WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); WREG32 963 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); WREG32 964 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); WREG32 965 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); WREG32 966 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); WREG32 967 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); WREG32 968 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); WREG32 969 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); WREG32 987 drivers/gpu/drm/radeon/rv770.c WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | WREG32 990 drivers/gpu/drm/radeon/rv770.c WREG32(VM_L2_CNTL2, 0); WREG32 991 drivers/gpu/drm/radeon/rv770.c WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); WREG32 997 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); WREG32 998 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); WREG32 999 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); WREG32 1000 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); WREG32 1001 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); WREG32 1002 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); WREG32 1003 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); WREG32 1005 drivers/gpu/drm/radeon/rv770.c WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); WREG32 1016 drivers/gpu/drm/radeon/rv770.c WREG32((0x2c14 + j), 0x00000000); WREG32 1017 drivers/gpu/drm/radeon/rv770.c WREG32((0x2c18 + j), 0x00000000); WREG32 1018 drivers/gpu/drm/radeon/rv770.c WREG32((0x2c1c + j), 0x00000000); WREG32 1019 drivers/gpu/drm/radeon/rv770.c WREG32((0x2c20 + j), 0x00000000); WREG32 1020 drivers/gpu/drm/radeon/rv770.c WREG32((0x2c24 + j), 0x00000000); WREG32 1032 drivers/gpu/drm/radeon/rv770.c WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); WREG32 1037 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 1039 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 1043 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 1045 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 1049 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 1051 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 1054 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); WREG32 1057 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_FB_LOCATION, tmp); WREG32 1058 drivers/gpu/drm/radeon/rv770.c WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); WREG32 1059 drivers/gpu/drm/radeon/rv770.c WREG32(HDP_NONSURFACE_INFO, (2 << 7)); WREG32 1060 drivers/gpu/drm/radeon/rv770.c WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); WREG32 1062 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); WREG32 1063 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); WREG32 1064 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); WREG32 1066 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_AGP_BASE, 0); WREG32 1067 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); WREG32 1068 drivers/gpu/drm/radeon/rv770.c WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); WREG32 1087 drivers/gpu/drm/radeon/rv770.c WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); WREG32 1088 drivers/gpu/drm/radeon/rv770.c WREG32(SCRATCH_UMSK, 0); WREG32 1101 drivers/gpu/drm/radeon/rv770.c WREG32(CP_RB_CNTL, WREG32 1108 drivers/gpu/drm/radeon/rv770.c WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); WREG32 1111 drivers/gpu/drm/radeon/rv770.c WREG32(GRBM_SOFT_RESET, 0); WREG32 1114 drivers/gpu/drm/radeon/rv770.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 1116 drivers/gpu/drm/radeon/rv770.c WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 1117 drivers/gpu/drm/radeon/rv770.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 1120 drivers/gpu/drm/radeon/rv770.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 1122 drivers/gpu/drm/radeon/rv770.c WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); WREG32 1124 drivers/gpu/drm/radeon/rv770.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 1125 drivers/gpu/drm/radeon/rv770.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 1126 drivers/gpu/drm/radeon/rv770.c WREG32(CP_ME_RAM_RADDR, 0); WREG32 1148 drivers/gpu/drm/radeon/rv770.c WREG32(CG_SPLL_FUNC_CNTL_2, tmp); WREG32 1157 drivers/gpu/drm/radeon/rv770.c WREG32(CG_SPLL_FUNC_CNTL_2, tmp); WREG32 1164 drivers/gpu/drm/radeon/rv770.c WREG32(MPLL_CNTL_MODE, tmp); WREG32 1292 drivers/gpu/drm/radeon/rv770.c WREG32((0x2c14 + j), 0x00000000); WREG32 1293 drivers/gpu/drm/radeon/rv770.c WREG32((0x2c18 + j), 0x00000000); WREG32 1294 drivers/gpu/drm/radeon/rv770.c WREG32((0x2c1c + j), 0x00000000); WREG32 1295 drivers/gpu/drm/radeon/rv770.c WREG32((0x2c20 + j), 0x00000000); WREG32 1296 drivers/gpu/drm/radeon/rv770.c WREG32((0x2c24 + j), 0x00000000); WREG32 1300 drivers/gpu/drm/radeon/rv770.c WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); WREG32 1314 drivers/gpu/drm/radeon/rv770.c WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); WREG32 1316 drivers/gpu/drm/radeon/rv770.c WREG32(SPI_CONFIG_CNTL, 0); WREG32 1379 drivers/gpu/drm/radeon/rv770.c WREG32(GB_TILING_CONFIG, gb_tiling_config); WREG32 1380 drivers/gpu/drm/radeon/rv770.c WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); WREG32 1381 drivers/gpu/drm/radeon/rv770.c WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); WREG32 1382 drivers/gpu/drm/radeon/rv770.c WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); WREG32 1383 drivers/gpu/drm/radeon/rv770.c WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); WREG32 1385 drivers/gpu/drm/radeon/rv770.c WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff)); WREG32 1386 drivers/gpu/drm/radeon/rv770.c WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff)); WREG32 1387 drivers/gpu/drm/radeon/rv770.c WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff)); WREG32 1390 drivers/gpu/drm/radeon/rv770.c WREG32(CGTS_SYS_TCC_DISABLE, 0); WREG32 1391 drivers/gpu/drm/radeon/rv770.c WREG32(CGTS_TCC_DISABLE, 0); WREG32 1392 drivers/gpu/drm/radeon/rv770.c WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); WREG32 1393 drivers/gpu/drm/radeon/rv770.c WREG32(CGTS_USER_TCC_DISABLE, 0); WREG32 1397 drivers/gpu/drm/radeon/rv770.c WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); WREG32 1398 drivers/gpu/drm/radeon/rv770.c WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); WREG32 1401 drivers/gpu/drm/radeon/rv770.c WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | WREG32 1404 drivers/gpu/drm/radeon/rv770.c WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); WREG32 1407 drivers/gpu/drm/radeon/rv770.c WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); WREG32 1411 drivers/gpu/drm/radeon/rv770.c WREG32(SX_DEBUG_1, sx_debug_1); WREG32 1416 drivers/gpu/drm/radeon/rv770.c WREG32(SMX_DC_CTL0, smx_dc_ctl0); WREG32 1419 drivers/gpu/drm/radeon/rv770.c WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | WREG32 1425 drivers/gpu/drm/radeon/rv770.c WREG32(SMX_SAR_CTL0, 0x00003f3f); WREG32 1440 drivers/gpu/drm/radeon/rv770.c WREG32(DB_DEBUG3, db_debug3); WREG32 1445 drivers/gpu/drm/radeon/rv770.c WREG32(DB_DEBUG4, db_debug4); WREG32 1448 drivers/gpu/drm/radeon/rv770.c WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | WREG32 1452 drivers/gpu/drm/radeon/rv770.c WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | WREG32 1456 drivers/gpu/drm/radeon/rv770.c WREG32(PA_SC_MULTI_CHIP_CNTL, 0); WREG32 1458 drivers/gpu/drm/radeon/rv770.c WREG32(VGT_NUM_INSTANCES, 1); WREG32 1460 drivers/gpu/drm/radeon/rv770.c WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); WREG32 1462 drivers/gpu/drm/radeon/rv770.c WREG32(CP_PERFMON_CNTL, 0); WREG32 1478 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); WREG32 1499 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_CONFIG, sq_config); WREG32 1501 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | WREG32 1505 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | WREG32 1515 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); WREG32 1517 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | WREG32 1520 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | WREG32 1528 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); WREG32 1529 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); WREG32 1530 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); WREG32 1531 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); WREG32 1532 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); WREG32 1533 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); WREG32 1534 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); WREG32 1535 drivers/gpu/drm/radeon/rv770.c WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); WREG32 1537 drivers/gpu/drm/radeon/rv770.c WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | WREG32 1541 drivers/gpu/drm/radeon/rv770.c WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | WREG32 1544 drivers/gpu/drm/radeon/rv770.c WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | WREG32 1566 drivers/gpu/drm/radeon/rv770.c WREG32(VGT_ES_PER_GS, 128); WREG32 1567 drivers/gpu/drm/radeon/rv770.c WREG32(VGT_GS_PER_ES, vgt_gs_per_es); WREG32 1568 drivers/gpu/drm/radeon/rv770.c WREG32(VGT_GS_PER_VS, 2); WREG32 1571 drivers/gpu/drm/radeon/rv770.c WREG32(VGT_GS_VERTEX_REUSE, 16); WREG32 1572 drivers/gpu/drm/radeon/rv770.c WREG32(PA_SC_LINE_STIPPLE_STATE, 0); WREG32 1573 drivers/gpu/drm/radeon/rv770.c WREG32(VGT_STRMOUT_EN, 0); WREG32 1574 drivers/gpu/drm/radeon/rv770.c WREG32(SX_MISC, 0); WREG32 1575 drivers/gpu/drm/radeon/rv770.c WREG32(PA_SC_MODE_CNTL, 0); WREG32 1576 drivers/gpu/drm/radeon/rv770.c WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); WREG32 1577 drivers/gpu/drm/radeon/rv770.c WREG32(PA_SC_AA_CONFIG, 0); WREG32 1578 drivers/gpu/drm/radeon/rv770.c WREG32(PA_SC_CLIPRECT_RULE, 0xffff); WREG32 1579 drivers/gpu/drm/radeon/rv770.c WREG32(PA_SC_LINE_STIPPLE, 0); WREG32 1580 drivers/gpu/drm/radeon/rv770.c WREG32(SPI_INPUT_Z, 0); WREG32 1581 drivers/gpu/drm/radeon/rv770.c WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); WREG32 1582 drivers/gpu/drm/radeon/rv770.c WREG32(CB_COLOR7_FRAG, 0); WREG32 1585 drivers/gpu/drm/radeon/rv770.c WREG32(CB_COLOR0_BASE, 0); WREG32 1586 drivers/gpu/drm/radeon/rv770.c WREG32(CB_COLOR1_BASE, 0); WREG32 1587 drivers/gpu/drm/radeon/rv770.c WREG32(CB_COLOR2_BASE, 0); WREG32 1588 drivers/gpu/drm/radeon/rv770.c WREG32(CB_COLOR3_BASE, 0); WREG32 1589 drivers/gpu/drm/radeon/rv770.c WREG32(CB_COLOR4_BASE, 0); WREG32 1590 drivers/gpu/drm/radeon/rv770.c WREG32(CB_COLOR5_BASE, 0); WREG32 1591 drivers/gpu/drm/radeon/rv770.c WREG32(CB_COLOR6_BASE, 0); WREG32 1592 drivers/gpu/drm/radeon/rv770.c WREG32(CB_COLOR7_BASE, 0); WREG32 1594 drivers/gpu/drm/radeon/rv770.c WREG32(TCP_CNTL, 0); WREG32 1597 drivers/gpu/drm/radeon/rv770.c WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); WREG32 1599 drivers/gpu/drm/radeon/rv770.c WREG32(PA_SC_MULTI_CHIP_CNTL, 0); WREG32 1601 drivers/gpu/drm/radeon/rv770.c WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | WREG32 1603 drivers/gpu/drm/radeon/rv770.c WREG32(VC_ENHANCE, 0); WREG32 2071 drivers/gpu/drm/radeon/rv770.c WREG32(0x541c, tmp | 0x8); WREG32 2072 drivers/gpu/drm/radeon/rv770.c WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); WREG32 2077 drivers/gpu/drm/radeon/rv770.c WREG32(MM_CFGREGS_CNTL, 0); WREG32 155 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_CGTT_LOCAL_0, mgcg_cgtt_local0); WREG32 156 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_CGTT_LOCAL_1, (RV770_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF)); WREG32 159 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CGTS_SM_CTRL_REG, RV770_MGCGCGTSSMCTRL_DFLT); WREG32 161 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_CGTT_LOCAL_0, 0xFFFFFFFF); WREG32 162 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_CGTT_LOCAL_1, 0xFFFFCFFF); WREG32 760 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(MC_ARB_SQM_RATIO, sqm_ratio); WREG32 767 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate); WREG32 809 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(MPLL_TIME, WREG32 835 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_BSP, pi->dsp); WREG32 850 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); WREG32 864 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_TPC, R600_TPC_DFLT); WREG32 869 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); WREG32 884 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32 891 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_FTV, pi->vrc); WREG32 896 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_FTV, 0); WREG32 1356 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32 1585 drivers/gpu/drm/radeon/rv770_dpm.c WREG32(S0_VID_LOWER_SMIO_CNTL, vid_smio_cntl); WREG32 290 drivers/gpu/drm/radeon/rv770_smc.c WREG32(SMC_SRAM_ADDR, addr); WREG32 320 drivers/gpu/drm/radeon/rv770_smc.c WREG32(SMC_SRAM_DATA, data); WREG32 353 drivers/gpu/drm/radeon/rv770_smc.c WREG32(SMC_SRAM_DATA, data); WREG32 386 drivers/gpu/drm/radeon/rv770_smc.c WREG32(SMC_ISR_FFD8_FFDB + i, tmp); WREG32 475 drivers/gpu/drm/radeon/rv770_smc.c WREG32(SMC_SRAM_DATA, 0); WREG32 627 drivers/gpu/drm/radeon/rv770_smc.c WREG32(SMC_SRAM_DATA, value); WREG32 1632 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_SUP_CNTL, 0x00000008); WREG32 1633 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_SUP_CNTL, 0x00000010); WREG32 1638 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); WREG32 1639 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); WREG32 1641 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); WREG32 1642 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); WREG32 1648 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); WREG32 1650 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); WREG32 1654 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_SUP_CNTL, 0x00000008); WREG32 1655 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_SUP_CNTL, 0x00000004); WREG32 1656 drivers/gpu/drm/radeon/si.c WREG32(MC_SEQ_SUP_CNTL, 0x00000001); WREG32 2004 drivers/gpu/drm/radeon/si.c WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, WREG32 2007 drivers/gpu/drm/radeon/si.c WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, WREG32 2439 drivers/gpu/drm/radeon/si.c WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); WREG32 2440 drivers/gpu/drm/radeon/si.c WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, WREG32 2447 drivers/gpu/drm/radeon/si.c WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); WREG32 2448 drivers/gpu/drm/radeon/si.c WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, WREG32 2452 drivers/gpu/drm/radeon/si.c WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); WREG32 2455 drivers/gpu/drm/radeon/si.c WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); WREG32 2456 drivers/gpu/drm/radeon/si.c WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); WREG32 2728 drivers/gpu/drm/radeon/si.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); WREG32 2943 drivers/gpu/drm/radeon/si.c WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); WREG32 2964 drivers/gpu/drm/radeon/si.c WREG32(GRBM_GFX_INDEX, data); WREG32 3014 drivers/gpu/drm/radeon/si.c WREG32(SPI_STATIC_THREAD_MGMT_3, data); WREG32 3088 drivers/gpu/drm/radeon/si.c WREG32(PA_SC_RASTER_CONFIG, data); WREG32 3193 drivers/gpu/drm/radeon/si.c WREG32((0x2c14 + j), 0x00000000); WREG32 3194 drivers/gpu/drm/radeon/si.c WREG32((0x2c18 + j), 0x00000000); WREG32 3195 drivers/gpu/drm/radeon/si.c WREG32((0x2c1c + j), 0x00000000); WREG32 3196 drivers/gpu/drm/radeon/si.c WREG32((0x2c20 + j), 0x00000000); WREG32 3197 drivers/gpu/drm/radeon/si.c WREG32((0x2c24 + j), 0x00000000); WREG32 3200 drivers/gpu/drm/radeon/si.c WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); WREG32 3201 drivers/gpu/drm/radeon/si.c WREG32(SRBM_INT_CNTL, 1); WREG32 3202 drivers/gpu/drm/radeon/si.c WREG32(SRBM_INT_ACK, 1); WREG32 3206 drivers/gpu/drm/radeon/si.c WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); WREG32 3278 drivers/gpu/drm/radeon/si.c WREG32(GB_ADDR_CONFIG, gb_addr_config); WREG32 3279 drivers/gpu/drm/radeon/si.c WREG32(DMIF_ADDR_CONFIG, gb_addr_config); WREG32 3280 drivers/gpu/drm/radeon/si.c WREG32(DMIF_ADDR_CALC, gb_addr_config); WREG32 3281 drivers/gpu/drm/radeon/si.c WREG32(HDP_ADDR_CONFIG, gb_addr_config); WREG32 3282 drivers/gpu/drm/radeon/si.c WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); WREG32 3283 drivers/gpu/drm/radeon/si.c WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); WREG32 3285 drivers/gpu/drm/radeon/si.c WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); WREG32 3286 drivers/gpu/drm/radeon/si.c WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); WREG32 3287 drivers/gpu/drm/radeon/si.c WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); WREG32 3309 drivers/gpu/drm/radeon/si.c WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | WREG32 3311 drivers/gpu/drm/radeon/si.c WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); WREG32 3314 drivers/gpu/drm/radeon/si.c WREG32(SX_DEBUG_1, sx_debug_1); WREG32 3316 drivers/gpu/drm/radeon/si.c WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); WREG32 3318 drivers/gpu/drm/radeon/si.c WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | WREG32 3323 drivers/gpu/drm/radeon/si.c WREG32(VGT_NUM_INSTANCES, 1); WREG32 3325 drivers/gpu/drm/radeon/si.c WREG32(CP_PERFMON_CNTL, 0); WREG32 3327 drivers/gpu/drm/radeon/si.c WREG32(SQ_CONFIG, 0); WREG32 3329 drivers/gpu/drm/radeon/si.c WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | WREG32 3332 drivers/gpu/drm/radeon/si.c WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | WREG32 3335 drivers/gpu/drm/radeon/si.c WREG32(VGT_GS_VERTEX_REUSE, 16); WREG32 3336 drivers/gpu/drm/radeon/si.c WREG32(PA_SC_LINE_STIPPLE_STATE, 0); WREG32 3338 drivers/gpu/drm/radeon/si.c WREG32(CB_PERFCOUNTER0_SELECT0, 0); WREG32 3339 drivers/gpu/drm/radeon/si.c WREG32(CB_PERFCOUNTER0_SELECT1, 0); WREG32 3340 drivers/gpu/drm/radeon/si.c WREG32(CB_PERFCOUNTER1_SELECT0, 0); WREG32 3341 drivers/gpu/drm/radeon/si.c WREG32(CB_PERFCOUNTER1_SELECT1, 0); WREG32 3342 drivers/gpu/drm/radeon/si.c WREG32(CB_PERFCOUNTER2_SELECT0, 0); WREG32 3343 drivers/gpu/drm/radeon/si.c WREG32(CB_PERFCOUNTER2_SELECT1, 0); WREG32 3344 drivers/gpu/drm/radeon/si.c WREG32(CB_PERFCOUNTER3_SELECT0, 0); WREG32 3345 drivers/gpu/drm/radeon/si.c WREG32(CB_PERFCOUNTER3_SELECT1, 0); WREG32 3349 drivers/gpu/drm/radeon/si.c WREG32(HDP_MISC_CNTL, tmp); WREG32 3352 drivers/gpu/drm/radeon/si.c WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); WREG32 3354 drivers/gpu/drm/radeon/si.c WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); WREG32 3467 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_CNTL, 0); WREG32 3471 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); WREG32 3472 drivers/gpu/drm/radeon/si.c WREG32(SCRATCH_UMSK, 0); WREG32 3507 drivers/gpu/drm/radeon/si.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 3509 drivers/gpu/drm/radeon/si.c WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 3510 drivers/gpu/drm/radeon/si.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 3516 drivers/gpu/drm/radeon/si.c WREG32(CP_CE_UCODE_ADDR, 0); WREG32 3518 drivers/gpu/drm/radeon/si.c WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 3519 drivers/gpu/drm/radeon/si.c WREG32(CP_CE_UCODE_ADDR, 0); WREG32 3525 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 3527 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); WREG32 3528 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 3534 drivers/gpu/drm/radeon/si.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 3536 drivers/gpu/drm/radeon/si.c WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 3537 drivers/gpu/drm/radeon/si.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 3541 drivers/gpu/drm/radeon/si.c WREG32(CP_CE_UCODE_ADDR, 0); WREG32 3543 drivers/gpu/drm/radeon/si.c WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 3544 drivers/gpu/drm/radeon/si.c WREG32(CP_CE_UCODE_ADDR, 0); WREG32 3548 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 3550 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); WREG32 3551 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 3554 drivers/gpu/drm/radeon/si.c WREG32(CP_PFP_UCODE_ADDR, 0); WREG32 3555 drivers/gpu/drm/radeon/si.c WREG32(CP_CE_UCODE_ADDR, 0); WREG32 3556 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_RAM_WADDR, 0); WREG32 3557 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_RAM_RADDR, 0); WREG32 3657 drivers/gpu/drm/radeon/si.c WREG32(CP_SEM_WAIT_TIMER, 0x0); WREG32 3658 drivers/gpu/drm/radeon/si.c WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); WREG32 3661 drivers/gpu/drm/radeon/si.c WREG32(CP_RB_WPTR_DELAY, 0); WREG32 3663 drivers/gpu/drm/radeon/si.c WREG32(CP_DEBUG, 0); WREG32 3664 drivers/gpu/drm/radeon/si.c WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); WREG32 3674 drivers/gpu/drm/radeon/si.c WREG32(CP_RB0_CNTL, tmp); WREG32 3677 drivers/gpu/drm/radeon/si.c WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); WREG32 3679 drivers/gpu/drm/radeon/si.c WREG32(CP_RB0_WPTR, ring->wptr); WREG32 3682 drivers/gpu/drm/radeon/si.c WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); WREG32 3683 drivers/gpu/drm/radeon/si.c WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); WREG32 3686 drivers/gpu/drm/radeon/si.c WREG32(SCRATCH_UMSK, 0xff); WREG32 3689 drivers/gpu/drm/radeon/si.c WREG32(SCRATCH_UMSK, 0); WREG32 3693 drivers/gpu/drm/radeon/si.c WREG32(CP_RB0_CNTL, tmp); WREG32 3695 drivers/gpu/drm/radeon/si.c WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); WREG32 3705 drivers/gpu/drm/radeon/si.c WREG32(CP_RB1_CNTL, tmp); WREG32 3708 drivers/gpu/drm/radeon/si.c WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); WREG32 3710 drivers/gpu/drm/radeon/si.c WREG32(CP_RB1_WPTR, ring->wptr); WREG32 3713 drivers/gpu/drm/radeon/si.c WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); WREG32 3714 drivers/gpu/drm/radeon/si.c WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); WREG32 3717 drivers/gpu/drm/radeon/si.c WREG32(CP_RB1_CNTL, tmp); WREG32 3719 drivers/gpu/drm/radeon/si.c WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); WREG32 3729 drivers/gpu/drm/radeon/si.c WREG32(CP_RB2_CNTL, tmp); WREG32 3732 drivers/gpu/drm/radeon/si.c WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); WREG32 3734 drivers/gpu/drm/radeon/si.c WREG32(CP_RB2_WPTR, ring->wptr); WREG32 3737 drivers/gpu/drm/radeon/si.c WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); WREG32 3738 drivers/gpu/drm/radeon/si.c WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); WREG32 3741 drivers/gpu/drm/radeon/si.c WREG32(CP_RB2_CNTL, tmp); WREG32 3743 drivers/gpu/drm/radeon/si.c WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); WREG32 3880 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); WREG32 3886 drivers/gpu/drm/radeon/si.c WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); WREG32 3892 drivers/gpu/drm/radeon/si.c WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); WREG32 3954 drivers/gpu/drm/radeon/si.c WREG32(GRBM_SOFT_RESET, tmp); WREG32 3960 drivers/gpu/drm/radeon/si.c WREG32(GRBM_SOFT_RESET, tmp); WREG32 3968 drivers/gpu/drm/radeon/si.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 3974 drivers/gpu/drm/radeon/si.c WREG32(SRBM_SOFT_RESET, tmp); WREG32 3993 drivers/gpu/drm/radeon/si.c WREG32(CG_SPLL_FUNC_CNTL, tmp); WREG32 3997 drivers/gpu/drm/radeon/si.c WREG32(CG_SPLL_FUNC_CNTL_2, tmp); WREG32 4007 drivers/gpu/drm/radeon/si.c WREG32(CG_SPLL_FUNC_CNTL_2, tmp); WREG32 4011 drivers/gpu/drm/radeon/si.c WREG32(MPLL_CNTL_MODE, tmp); WREG32 4020 drivers/gpu/drm/radeon/si.c WREG32(SPLL_CNTL_MODE, tmp); WREG32 4024 drivers/gpu/drm/radeon/si.c WREG32(CG_SPLL_FUNC_CNTL, tmp); WREG32 4028 drivers/gpu/drm/radeon/si.c WREG32(CG_SPLL_FUNC_CNTL, tmp); WREG32 4032 drivers/gpu/drm/radeon/si.c WREG32(SPLL_CNTL_MODE, tmp); WREG32 4049 drivers/gpu/drm/radeon/si.c WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); WREG32 4053 drivers/gpu/drm/radeon/si.c WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); WREG32 4057 drivers/gpu/drm/radeon/si.c WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); WREG32 4149 drivers/gpu/drm/radeon/si.c WREG32((0x2c14 + j), 0x00000000); WREG32 4150 drivers/gpu/drm/radeon/si.c WREG32((0x2c18 + j), 0x00000000); WREG32 4151 drivers/gpu/drm/radeon/si.c WREG32((0x2c1c + j), 0x00000000); WREG32 4152 drivers/gpu/drm/radeon/si.c WREG32((0x2c20 + j), 0x00000000); WREG32 4153 drivers/gpu/drm/radeon/si.c WREG32((0x2c24 + j), 0x00000000); WREG32 4155 drivers/gpu/drm/radeon/si.c WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); WREG32 4163 drivers/gpu/drm/radeon/si.c WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); WREG32 4165 drivers/gpu/drm/radeon/si.c WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, WREG32 4167 drivers/gpu/drm/radeon/si.c WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32 4169 drivers/gpu/drm/radeon/si.c WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, WREG32 4173 drivers/gpu/drm/radeon/si.c WREG32(MC_VM_FB_LOCATION, tmp); WREG32 4175 drivers/gpu/drm/radeon/si.c WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); WREG32 4176 drivers/gpu/drm/radeon/si.c WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); WREG32 4177 drivers/gpu/drm/radeon/si.c WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); WREG32 4178 drivers/gpu/drm/radeon/si.c WREG32(MC_VM_AGP_BASE, 0); WREG32 4179 drivers/gpu/drm/radeon/si.c WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); WREG32 4180 drivers/gpu/drm/radeon/si.c WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); WREG32 4279 drivers/gpu/drm/radeon/si.c WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); WREG32 4282 drivers/gpu/drm/radeon/si.c WREG32(VM_INVALIDATE_REQUEST, 1); WREG32 4297 drivers/gpu/drm/radeon/si.c WREG32(MC_VM_MX_L1_TLB_CNTL, WREG32 4305 drivers/gpu/drm/radeon/si.c WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | WREG32 4311 drivers/gpu/drm/radeon/si.c WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); WREG32 4312 drivers/gpu/drm/radeon/si.c WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | WREG32 4316 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); WREG32 4317 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); WREG32 4318 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); WREG32 4319 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 4321 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT0_CNTL2, 0); WREG32 4322 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | WREG32 4325 drivers/gpu/drm/radeon/si.c WREG32(0x15D4, 0); WREG32 4326 drivers/gpu/drm/radeon/si.c WREG32(0x15D8, 0); WREG32 4327 drivers/gpu/drm/radeon/si.c WREG32(0x15DC, 0); WREG32 4331 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); WREG32 4332 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); WREG32 4339 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), WREG32 4342 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), WREG32 4347 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, WREG32 4349 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT1_CNTL2, 4); WREG32 4350 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | WREG32 4387 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT0_CNTL, 0); WREG32 4388 drivers/gpu/drm/radeon/si.c WREG32(VM_CONTEXT1_CNTL, 0); WREG32 4390 drivers/gpu/drm/radeon/si.c WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | WREG32 4393 drivers/gpu/drm/radeon/si.c WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | WREG32 4397 drivers/gpu/drm/radeon/si.c WREG32(VM_L2_CNTL2, 0); WREG32 4398 drivers/gpu/drm/radeon/si.c WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | WREG32 5156 drivers/gpu/drm/radeon/si.c WREG32(CP_INT_CNTL_RING0, tmp); WREG32 5188 drivers/gpu/drm/radeon/si.c WREG32(UVD_CGC_CTRL, tmp); WREG32 5201 drivers/gpu/drm/radeon/si.c WREG32(UVD_CGC_CTRL, tmp); WREG32 5213 drivers/gpu/drm/radeon/si.c WREG32(RLC_CNTL, data); WREG32 5227 drivers/gpu/drm/radeon/si.c WREG32(RLC_CNTL, rlc); WREG32 5240 drivers/gpu/drm/radeon/si.c WREG32(DMA_PG, data); WREG32 5247 drivers/gpu/drm/radeon/si.c WREG32(DMA_PGFSM_WRITE, 0x00002000); WREG32 5248 drivers/gpu/drm/radeon/si.c WREG32(DMA_PGFSM_CONFIG, 0x100010ff); WREG32 5251 drivers/gpu/drm/radeon/si.c WREG32(DMA_PGFSM_WRITE, 0); WREG32 5261 drivers/gpu/drm/radeon/si.c WREG32(RLC_TTOP_D, tmp); WREG32 5265 drivers/gpu/drm/radeon/si.c WREG32(RLC_PG_CNTL, tmp); WREG32 5269 drivers/gpu/drm/radeon/si.c WREG32(RLC_AUTO_PG_CTRL, tmp); WREG32 5273 drivers/gpu/drm/radeon/si.c WREG32(RLC_AUTO_PG_CTRL, tmp); WREG32 5283 drivers/gpu/drm/radeon/si.c WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); WREG32 5287 drivers/gpu/drm/radeon/si.c WREG32(RLC_PG_CNTL, tmp); WREG32 5289 drivers/gpu/drm/radeon/si.c WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); WREG32 5296 drivers/gpu/drm/radeon/si.c WREG32(RLC_AUTO_PG_CTRL, tmp); WREG32 5347 drivers/gpu/drm/radeon/si.c WREG32(RLC_PG_AO_CU_MASK, tmp); WREG32 5352 drivers/gpu/drm/radeon/si.c WREG32(RLC_MAX_PG_CU, tmp); WREG32 5365 drivers/gpu/drm/radeon/si.c WREG32(RLC_GCPM_GENERAL_3, 0x00000080); WREG32 5369 drivers/gpu/drm/radeon/si.c WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); WREG32 5370 drivers/gpu/drm/radeon/si.c WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); WREG32 5371 drivers/gpu/drm/radeon/si.c WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff); WREG32 5377 drivers/gpu/drm/radeon/si.c WREG32(RLC_SERDES_WR_CTRL, 0x007000ff); WREG32 5392 drivers/gpu/drm/radeon/si.c WREG32(RLC_CGCG_CGLS_CTRL, data); WREG32 5404 drivers/gpu/drm/radeon/si.c WREG32(CGTS_SM_CTRL_REG, data); WREG32 5410 drivers/gpu/drm/radeon/si.c WREG32(CP_MEM_SLP_CNTL, data); WREG32 5416 drivers/gpu/drm/radeon/si.c WREG32(RLC_CGTT_MGCG_OVERRIDE, data); WREG32 5420 drivers/gpu/drm/radeon/si.c WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); WREG32 5421 drivers/gpu/drm/radeon/si.c WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); WREG32 5422 drivers/gpu/drm/radeon/si.c WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff); WREG32 5429 drivers/gpu/drm/radeon/si.c WREG32(RLC_CGTT_MGCG_OVERRIDE, data); WREG32 5434 drivers/gpu/drm/radeon/si.c WREG32(CP_MEM_SLP_CNTL, data); WREG32 5439 drivers/gpu/drm/radeon/si.c WREG32(CGTS_SM_CTRL_REG, data); WREG32 5443 drivers/gpu/drm/radeon/si.c WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); WREG32 5444 drivers/gpu/drm/radeon/si.c WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); WREG32 5445 drivers/gpu/drm/radeon/si.c WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff); WREG32 5464 drivers/gpu/drm/radeon/si.c WREG32(UVD_CGC_CTRL, data); WREG32 5476 drivers/gpu/drm/radeon/si.c WREG32(UVD_CGC_CTRL, data); WREG32 5509 drivers/gpu/drm/radeon/si.c WREG32(mc_cg_registers[i], data); WREG32 5526 drivers/gpu/drm/radeon/si.c WREG32(mc_cg_registers[i], data); WREG32 5545 drivers/gpu/drm/radeon/si.c WREG32(DMA_POWER_CNTL + offset, data); WREG32 5546 drivers/gpu/drm/radeon/si.c WREG32(DMA_CLK_CTRL + offset, 0x00000100); WREG32 5557 drivers/gpu/drm/radeon/si.c WREG32(DMA_POWER_CNTL + offset, data); WREG32 5562 drivers/gpu/drm/radeon/si.c WREG32(DMA_CLK_CTRL + offset, data); WREG32 5598 drivers/gpu/drm/radeon/si.c WREG32(HDP_HOST_PATH_CNTL, data); WREG32 5614 drivers/gpu/drm/radeon/si.c WREG32(HDP_MEM_POWER_LS, data); WREG32 5785 drivers/gpu/drm/radeon/si.c WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); WREG32 5786 drivers/gpu/drm/radeon/si.c WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); WREG32 5791 drivers/gpu/drm/radeon/si.c WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); WREG32 5792 drivers/gpu/drm/radeon/si.c WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); WREG32 5812 drivers/gpu/drm/radeon/si.c WREG32(GRBM_SOFT_RESET, tmp); WREG32 5815 drivers/gpu/drm/radeon/si.c WREG32(GRBM_SOFT_RESET, tmp); WREG32 5821 drivers/gpu/drm/radeon/si.c WREG32(RLC_CNTL, 0); WREG32 5830 drivers/gpu/drm/radeon/si.c WREG32(RLC_CNTL, RLC_ENABLE); WREG32 5857 drivers/gpu/drm/radeon/si.c WREG32(RLC_LB_CNTL, tmp); WREG32 5861 drivers/gpu/drm/radeon/si.c WREG32(SPI_LB_CU_MASK, 0x00ff); WREG32 5880 drivers/gpu/drm/radeon/si.c WREG32(RLC_RL_BASE, 0); WREG32 5881 drivers/gpu/drm/radeon/si.c WREG32(RLC_RL_SIZE, 0); WREG32 5882 drivers/gpu/drm/radeon/si.c WREG32(RLC_LB_CNTL, 0); WREG32 5883 drivers/gpu/drm/radeon/si.c WREG32(RLC_LB_CNTR_MAX, 0xffffffff); WREG32 5884 drivers/gpu/drm/radeon/si.c WREG32(RLC_LB_CNTR_INIT, 0); WREG32 5885 drivers/gpu/drm/radeon/si.c WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); WREG32 5887 drivers/gpu/drm/radeon/si.c WREG32(RLC_MC_CNTL, 0); WREG32 5888 drivers/gpu/drm/radeon/si.c WREG32(RLC_UCODE_CNTL, 0); WREG32 5900 drivers/gpu/drm/radeon/si.c WREG32(RLC_UCODE_ADDR, i); WREG32 5901 drivers/gpu/drm/radeon/si.c WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++)); WREG32 5907 drivers/gpu/drm/radeon/si.c WREG32(RLC_UCODE_ADDR, i); WREG32 5908 drivers/gpu/drm/radeon/si.c WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); WREG32 5911 drivers/gpu/drm/radeon/si.c WREG32(RLC_UCODE_ADDR, 0); WREG32 5927 drivers/gpu/drm/radeon/si.c WREG32(IH_CNTL, ih_cntl); WREG32 5928 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 5939 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 5940 drivers/gpu/drm/radeon/si.c WREG32(IH_CNTL, ih_cntl); WREG32 5942 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_RPTR, 0); WREG32 5943 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_WPTR, 0); WREG32 5955 drivers/gpu/drm/radeon/si.c WREG32(CP_INT_CNTL_RING0, tmp); WREG32 5956 drivers/gpu/drm/radeon/si.c WREG32(CP_INT_CNTL_RING1, 0); WREG32 5957 drivers/gpu/drm/radeon/si.c WREG32(CP_INT_CNTL_RING2, 0); WREG32 5959 drivers/gpu/drm/radeon/si.c WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); WREG32 5961 drivers/gpu/drm/radeon/si.c WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); WREG32 5962 drivers/gpu/drm/radeon/si.c WREG32(GRBM_INT_CNTL, 0); WREG32 5963 drivers/gpu/drm/radeon/si.c WREG32(SRBM_INT_CNTL, 0); WREG32 5965 drivers/gpu/drm/radeon/si.c WREG32(INT_MASK + crtc_offsets[i], 0); WREG32 5967 drivers/gpu/drm/radeon/si.c WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); WREG32 5970 drivers/gpu/drm/radeon/si.c WREG32(DAC_AUTODETECT_INT_CONTROL, 0); WREG32 6001 drivers/gpu/drm/radeon/si.c WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); WREG32 6009 drivers/gpu/drm/radeon/si.c WREG32(INTERRUPT_CNTL, interrupt_cntl); WREG32 6011 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); WREG32 6022 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); WREG32 6023 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); WREG32 6025 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32 6028 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_RPTR, 0); WREG32 6029 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_WPTR, 0); WREG32 6036 drivers/gpu/drm/radeon/si.c WREG32(IH_CNTL, ih_cntl); WREG32 6103 drivers/gpu/drm/radeon/si.c WREG32(CP_INT_CNTL_RING0, cp_int_cntl); WREG32 6104 drivers/gpu/drm/radeon/si.c WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); WREG32 6105 drivers/gpu/drm/radeon/si.c WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); WREG32 6107 drivers/gpu/drm/radeon/si.c WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); WREG32 6108 drivers/gpu/drm/radeon/si.c WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); WREG32 6110 drivers/gpu/drm/radeon/si.c WREG32(GRBM_INT_CNTL, grbm_int_cntl); WREG32 6125 drivers/gpu/drm/radeon/si.c WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); WREG32 6136 drivers/gpu/drm/radeon/si.c WREG32(CG_THERMAL_INT, thermal_int); WREG32 6164 drivers/gpu/drm/radeon/si.c WREG32(GRPH_INT_STATUS + crtc_offsets[j], WREG32 6170 drivers/gpu/drm/radeon/si.c WREG32(VBLANK_STATUS + crtc_offsets[j], WREG32 6173 drivers/gpu/drm/radeon/si.c WREG32(VLINE_STATUS + crtc_offsets[j], WREG32 6230 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_CNTL, tmp); WREG32 6364 drivers/gpu/drm/radeon/si.c WREG32(SRBM_INT_ACK, 0x1); WREG32 6437 drivers/gpu/drm/radeon/si.c WREG32(IH_RB_RPTR, rptr); WREG32 6990 drivers/gpu/drm/radeon/si.c WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); WREG32 7399 drivers/gpu/drm/radeon/si.c WREG32(THM_CLK_CNTL, data); WREG32 7405 drivers/gpu/drm/radeon/si.c WREG32(MISC_CLK_CNTL, data); WREG32 7410 drivers/gpu/drm/radeon/si.c WREG32(CG_CLKPIN_CNTL, data); WREG32 7415 drivers/gpu/drm/radeon/si.c WREG32(CG_CLKPIN_CNTL_2, data); WREG32 7421 drivers/gpu/drm/radeon/si.c WREG32(MPLL_BYPASSCLK_SEL, data); WREG32 7426 drivers/gpu/drm/radeon/si.c WREG32(SPLL_CNTL_MODE, data); WREG32 2674 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_CAC_CTRL, reg); WREG32 2769 drivers/gpu/drm/radeon/si_dpm.c WREG32(config_regs->offset << 2, data); WREG32 3216 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); WREG32 3388 drivers/gpu/drm/radeon/si_dpm.c WREG32(SMC_SCRATCH0, parameter); WREG32 3606 drivers/gpu/drm/radeon/si_dpm.c WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); WREG32 3617 drivers/gpu/drm/radeon/si_dpm.c WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); WREG32 3698 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32 3717 drivers/gpu/drm/radeon/si_dpm.c WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); WREG32 3761 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_BSP, pi->dsp); WREG32 3775 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); WREG32 3791 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_TPC, R600_TPC_DFLT); WREG32 3796 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); WREG32 3810 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_DISPLAY_GAP_CNTL, tmp); WREG32 3817 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FTV, pi->vrc); WREG32 3822 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FTV, 0); WREG32 4768 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); WREG32 4769 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); WREG32 5545 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); WREG32 5546 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); WREG32 5547 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); WREG32 5548 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); WREG32 5549 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); WREG32 5550 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); WREG32 5551 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); WREG32 5552 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); WREG32 5553 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); WREG32 5554 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); WREG32 5555 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); WREG32 5556 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); WREG32 5557 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); WREG32 5558 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); WREG32 5967 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_THERMAL_INT, thermal_int); WREG32 5976 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_THERMAL_INT, thermal_int); WREG32 6023 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); WREG32 6027 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); WREG32 6189 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL0, tmp); WREG32 6266 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_TACH_CTRL, tmp); WREG32 6282 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); WREG32 6286 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); WREG32 6306 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_TACH_CTRL, tmp); WREG32 6311 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_FDO_CTRL2, tmp); WREG32 41 drivers/gpu/drm/radeon/si_smc.c WREG32(SMC_IND_INDEX_0, smc_address); WREG32 71 drivers/gpu/drm/radeon/si_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 104 drivers/gpu/drm/radeon/si_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 180 drivers/gpu/drm/radeon/si_smc.c WREG32(SMC_MESSAGE_0, msg); WREG32 265 drivers/gpu/drm/radeon/si_smc.c WREG32(SMC_IND_INDEX_0, ucode_start_address); WREG32 271 drivers/gpu/drm/radeon/si_smc.c WREG32(SMC_IND_DATA_0, data); WREG32 306 drivers/gpu/drm/radeon/si_smc.c WREG32(SMC_IND_DATA_0, value); WREG32 112 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); WREG32 113 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); WREG32 115 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); WREG32 116 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); WREG32 139 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u)); WREG32 170 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_SCRATCH2, 0x01B60A17); WREG32 337 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_BSP_0, pi->psp); WREG32 355 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_BSP_0 + (i * 4), pi->dsp); WREG32 357 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_BSP_0 + (i * 4), pi->psp); WREG32 360 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp); WREG32 367 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_AT_0, value); WREG32 369 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_AT_1, value); WREG32 371 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_AT_2, value); WREG32 373 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_AT_3, value); WREG32 375 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_AT_4, value); WREG32 377 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_AT_5, value); WREG32 379 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_AT_6, value); WREG32 381 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_AT_7, value); WREG32 454 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_FTV, vrc); WREG32 459 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_FTV, 0); WREG32 470 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_SSP, SSTU(u) | SST(p)); WREG32 503 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl); WREG32 517 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl); WREG32 527 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl); WREG32 543 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); WREG32 748 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4); WREG32 808 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4); WREG32 884 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(DOUT_SCRATCH3, v); WREG32 903 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2); WREG32 904 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl); WREG32 937 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5); WREG32 948 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3); WREG32 981 drivers/gpu/drm/radeon/sumo_dpm.c WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4); WREG32 47 drivers/gpu/drm/radeon/sumo_smc.c WREG32(GFX_INT_REQ, gfx_int_req); WREG32 68 drivers/gpu/drm/radeon/sumo_smc.c WREG32(GFX_INT_REQ, gfx_int_req); WREG32 388 drivers/gpu/drm/radeon/trinity_dpm.c WREG32(CG_PG_CTRL, SP(p) | SU(u)); WREG32 418 drivers/gpu/drm/radeon/trinity_dpm.c WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_ENABLE); WREG32 420 drivers/gpu/drm/radeon/trinity_dpm.c WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_DISABLE); WREG32 471 drivers/gpu/drm/radeon/trinity_dpm.c WREG32(seq[i], seq[i+1]); WREG32 942 drivers/gpu/drm/radeon/trinity_dpm.c WREG32(CG_MISC_REG, tmp); WREG32 34 drivers/gpu/drm/radeon/trinity_smc.c WREG32(SMC_MESSAGE_0, id); WREG32 115 drivers/gpu/drm/radeon/trinity_smc.c WREG32(SMC_INT_REQ, 1); WREG32 125 drivers/gpu/drm/radeon/trinity_smc.c WREG32(SMC_INT_REQ, 0); WREG32 70 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_RBC_RB_WPTR, ring->wptr); WREG32 123 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_VCPU_CACHE_OFFSET0, addr); WREG32 124 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_VCPU_CACHE_SIZE0, size); WREG32 128 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_VCPU_CACHE_OFFSET1, addr); WREG32 129 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_VCPU_CACHE_SIZE1, size); WREG32 134 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_VCPU_CACHE_OFFSET2, addr); WREG32 135 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_VCPU_CACHE_SIZE2, size); WREG32 139 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); WREG32 143 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); WREG32 145 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); WREG32 217 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(MC_CONFIG, 0); WREG32 218 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(MC_CONFIG, 1 << 4); WREG32 219 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(RS_DQ_RD_RET_CONF, 0x3f); WREG32 220 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(MC_CONFIG, 0x1f); WREG32 274 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_CGC_GATE, 0); WREG32 285 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET | WREG32 295 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | WREG32 303 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl); WREG32 304 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl); WREG32 306 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_MPC_SET_MUXA0, 0x40c2040); WREG32 307 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_MPC_SET_MUXA1, 0x0); WREG32 308 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_MPC_SET_MUXB0, 0x40c2040); WREG32 309 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_MPC_SET_MUXB1, 0x0); WREG32 310 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_MPC_SET_ALU, 0); WREG32 311 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_MPC_SET_MUX, 0x88); WREG32 314 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); WREG32 318 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_VCPU_CNTL, 1 << 9); WREG32 326 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_SOFT_RESET, 0); WREG32 358 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_RBC_RB_CNTL, 0x11010101); WREG32 361 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_RBC_RB_WPTR_CNTL, 0); WREG32 364 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | WREG32 368 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_RBC_RB_RPTR, 0x0); WREG32 371 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_RBC_RB_WPTR, ring->wptr); WREG32 374 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); WREG32 394 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_RBC_RB_CNTL, 0x11010101); WREG32 402 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET); WREG32 406 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_VCPU_CNTL, 0x0); WREG32 427 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD); WREG32 115 drivers/gpu/drm/radeon/uvd_v2_2.c WREG32(UVD_VCPU_CACHE_OFFSET0, addr); WREG32 116 drivers/gpu/drm/radeon/uvd_v2_2.c WREG32(UVD_VCPU_CACHE_SIZE0, size); WREG32 120 drivers/gpu/drm/radeon/uvd_v2_2.c WREG32(UVD_VCPU_CACHE_OFFSET1, addr); WREG32 121 drivers/gpu/drm/radeon/uvd_v2_2.c WREG32(UVD_VCPU_CACHE_SIZE1, size); WREG32 126 drivers/gpu/drm/radeon/uvd_v2_2.c WREG32(UVD_VCPU_CACHE_OFFSET2, addr); WREG32 127 drivers/gpu/drm/radeon/uvd_v2_2.c WREG32(UVD_VCPU_CACHE_SIZE2, size); WREG32 131 drivers/gpu/drm/radeon/uvd_v2_2.c WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); WREG32 135 drivers/gpu/drm/radeon/uvd_v2_2.c WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); WREG32 196 drivers/gpu/drm/radeon/uvd_v2_2.c WREG32(UVD_VCPU_CHIP_ID, chip_id); WREG32 52 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_VCPU_CACHE_OFFSET0, addr); WREG32 53 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_VCPU_CACHE_SIZE0, size); WREG32 57 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_VCPU_CACHE_OFFSET1, addr); WREG32 58 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_VCPU_CACHE_SIZE1, size); WREG32 63 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_VCPU_CACHE_OFFSET2, addr); WREG32 64 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_VCPU_CACHE_SIZE2, size); WREG32 68 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); WREG32 72 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); WREG32 75 drivers/gpu/drm/radeon/uvd_v4_2.c WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles); WREG32 97 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_WPTR, ring->wptr); WREG32 99 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_WPTR2, ring->wptr); WREG32 109 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_CLOCK_GATING_A, tmp); WREG32 114 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_UENC_CLOCK_GATING, tmp); WREG32 118 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); WREG32 122 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_CLOCK_GATING_A, tmp); WREG32 127 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_UENC_CLOCK_GATING, tmp); WREG32 131 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); WREG32 141 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_CLOCK_GATING_A, tmp); WREG32 146 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_CLOCK_GATING_B, tmp); WREG32 150 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_UENC_CLOCK_GATING, tmp); WREG32 154 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); WREG32 225 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_CLOCK_GATING_B, 0); WREG32 229 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_LMI_CTRL, 0x00398000); WREG32 231 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_LMI_SWAP_CNTL, 0); WREG32 232 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_LMI_SWAP_CNTL1, 0); WREG32 233 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_LMI_VM_CTRL, 0); WREG32 235 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES); WREG32 239 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); WREG32 240 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_VCPU_CACHE_SIZE0, size); WREG32 244 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); WREG32 245 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_VCPU_CACHE_SIZE1, size); WREG32 249 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); WREG32 250 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_VCPU_CACHE_SIZE2, size); WREG32 254 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect); WREG32 298 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_RPTR, ring->wptr); WREG32 299 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_WPTR, ring->wptr); WREG32 300 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_BASE_LO, ring->gpu_addr); WREG32 301 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); WREG32 302 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_SIZE, ring->ring_size / 4); WREG32 305 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_RPTR2, ring->wptr); WREG32 306 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_WPTR2, ring->wptr); WREG32 307 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); WREG32 308 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); WREG32 309 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_SIZE2, ring->ring_size / 4); WREG32 45 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_CLOCK_GATING_B, tmp); WREG32 49 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_UENC_CLOCK_GATING, tmp); WREG32 53 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); WREG32 55 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_CGTT_CLK_OVERRIDE, 0); WREG32 60 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_CLOCK_GATING_B, tmp); WREG32 65 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_UENC_CLOCK_GATING, tmp); WREG32 69 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); WREG32 85 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_CLOCK_GATING_B, tmp); WREG32 91 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_UENC_CLOCK_GATING, tmp); WREG32 96 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); WREG32 99 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_CGTT_CLK_OVERRIDE, 0); WREG32 104 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_CGTT_CLK_OVERRIDE, 7); WREG32 138 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_CLOCK_GATING_A, tmp); WREG32 143 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_UENC_CLOCK_GATING, tmp); WREG32 148 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_CLOCK_GATING_B, tmp); WREG32 165 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_CLOCK_GATING_B, 0xf7); WREG32 167 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_LMI_CTRL, 0x00398000); WREG32 169 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_LMI_SWAP_CNTL, 0); WREG32 170 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_LMI_SWAP_CNTL1, 0); WREG32 171 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_LMI_VM_CTRL, 0); WREG32 173 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8); WREG32 177 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); WREG32 178 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_VCPU_CACHE_SIZE0, size); WREG32 182 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); WREG32 183 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_VCPU_CACHE_SIZE1, size); WREG32 187 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); WREG32 188 drivers/gpu/drm/radeon/vce_v2_0.c WREG32(VCE_VCPU_CACHE_SIZE2, size); WREG32 546 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED); WREG32 548 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED); WREG32 611 drivers/misc/habanalabs/goya/goya.c WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size)); WREG32 620 drivers/misc/habanalabs/goya/goya.c WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, WREG32 782 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address)); WREG32 783 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address)); WREG32 785 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH)); WREG32 786 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); WREG32 787 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); WREG32 789 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); WREG32 790 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); WREG32 791 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); WREG32 792 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); WREG32 793 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); WREG32 794 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); WREG32 795 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off, WREG32 799 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002); WREG32 800 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008); WREG32 803 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED); WREG32 805 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED); WREG32 807 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, QMAN_DMA_ERR_MSG_EN); WREG32 808 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE); WREG32 822 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo); WREG32 823 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi); WREG32 824 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off, WREG32 833 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr)); WREG32 834 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001); WREG32 877 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_CFG0, 0); WREG32 878 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_1_GLBL_CFG0, 0); WREG32 879 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_2_GLBL_CFG0, 0); WREG32 880 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_3_GLBL_CFG0, 0); WREG32 881 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_4_GLBL_CFG0, 0); WREG32 892 drivers/misc/habanalabs/goya/goya.c WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); WREG32 1020 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address)); WREG32 1021 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address)); WREG32 1023 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address)); WREG32 1024 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address)); WREG32 1026 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_CQ_BASE_ADDR_LOW, WREG32 1028 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_CQ_BASE_ADDR_HIGH, WREG32 1031 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES); WREG32 1032 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES); WREG32 1033 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE); WREG32 1036 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_EQ_CI, 0); WREG32 1038 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_IF_PF_PQ_PI, 0); WREG32 1040 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP); WREG32 1042 drivers/misc/habanalabs/goya/goya.c WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, WREG32 1065 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_PLL_DIV_SEL_0, 0x0); WREG32 1066 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_PLL_DIV_SEL_1, 0x0); WREG32 1067 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_PLL_DIV_SEL_2, 0x0); WREG32 1068 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_PLL_DIV_SEL_3, 0x0); WREG32 1070 drivers/misc/habanalabs/goya/goya.c WREG32(mmIC_PLL_DIV_SEL_0, 0x0); WREG32 1071 drivers/misc/habanalabs/goya/goya.c WREG32(mmIC_PLL_DIV_SEL_1, 0x0); WREG32 1072 drivers/misc/habanalabs/goya/goya.c WREG32(mmIC_PLL_DIV_SEL_2, 0x0); WREG32 1073 drivers/misc/habanalabs/goya/goya.c WREG32(mmIC_PLL_DIV_SEL_3, 0x0); WREG32 1075 drivers/misc/habanalabs/goya/goya.c WREG32(mmMC_PLL_DIV_SEL_0, 0x0); WREG32 1076 drivers/misc/habanalabs/goya/goya.c WREG32(mmMC_PLL_DIV_SEL_1, 0x0); WREG32 1077 drivers/misc/habanalabs/goya/goya.c WREG32(mmMC_PLL_DIV_SEL_2, 0x0); WREG32 1078 drivers/misc/habanalabs/goya/goya.c WREG32(mmMC_PLL_DIV_SEL_3, 0x0); WREG32 1080 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0); WREG32 1081 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0); WREG32 1082 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0); WREG32 1083 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0); WREG32 1085 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0); WREG32 1086 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0); WREG32 1087 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0); WREG32 1088 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0); WREG32 1090 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0); WREG32 1091 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0); WREG32 1092 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0); WREG32 1093 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0); WREG32 1095 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC_PLL_DIV_SEL_0, 0x0); WREG32 1096 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC_PLL_DIV_SEL_1, 0x0); WREG32 1097 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC_PLL_DIV_SEL_2, 0x0); WREG32 1098 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC_PLL_DIV_SEL_3, 0x0); WREG32 1103 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010); WREG32 1104 drivers/misc/habanalabs/goya/goya.c WREG32(mmIC_PLL_CLK_RLX_0, 0x100010); WREG32 1128 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000); WREG32 1130 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF); WREG32 1131 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F); WREG32 1132 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF); WREG32 1133 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF); WREG32 1134 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF); WREG32 1135 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF); WREG32 1136 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF); WREG32 1137 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF); WREG32 1138 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF); WREG32 1139 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF); WREG32 1167 drivers/misc/habanalabs/goya/goya.c WREG32(tpc_slm_offset + (slm_index << 2), 0); WREG32 1223 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); WREG32 1224 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); WREG32 1225 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); WREG32 1226 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); WREG32 1227 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302); WREG32 1229 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204); WREG32 1230 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204); WREG32 1231 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204); WREG32 1232 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204); WREG32 1233 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204); WREG32 1236 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206); WREG32 1237 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206); WREG32 1238 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206); WREG32 1239 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207); WREG32 1240 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207); WREG32 1242 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207); WREG32 1243 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207); WREG32 1244 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206); WREG32 1245 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206); WREG32 1246 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206); WREG32 1248 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101); WREG32 1249 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102); WREG32 1250 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103); WREG32 1251 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104); WREG32 1252 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105); WREG32 1254 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105); WREG32 1255 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104); WREG32 1256 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103); WREG32 1257 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102); WREG32 1258 drivers/misc/habanalabs/goya/goya.c WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101); WREG32 1261 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_STORE_MAX_CREDIT, 0x21); WREG32 1262 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_AGU, 0x0f0f0f10); WREG32 1263 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_SEI_MASK, ~0x0); WREG32 1265 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101); WREG32 1266 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101); WREG32 1267 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101); WREG32 1268 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101); WREG32 1269 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101); WREG32 1270 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701); WREG32 1271 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401); WREG32 1272 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401); WREG32 1273 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301); WREG32 1274 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101); WREG32 1275 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101); WREG32 1276 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105); WREG32 1277 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501); WREG32 1278 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501); WREG32 1279 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301); WREG32 1280 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401); WREG32 1281 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101); WREG32 1282 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101); WREG32 1283 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202); WREG32 1284 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101); WREG32 1285 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201); WREG32 1286 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701); WREG32 1287 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101); WREG32 1288 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101); WREG32 1289 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101); WREG32 1290 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101); WREG32 1291 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701); WREG32 1292 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201); WREG32 1293 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101); WREG32 1294 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102); WREG32 1295 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701); WREG32 1296 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701); WREG32 1297 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707); WREG32 1298 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201); WREG32 1299 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201); WREG32 1300 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201); WREG32 1301 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102); WREG32 1302 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102); WREG32 1303 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102); WREG32 1304 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102); WREG32 1305 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102); WREG32 1306 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107); WREG32 1307 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106); WREG32 1308 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102); WREG32 1309 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102); WREG32 1310 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102); WREG32 1311 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102); WREG32 1312 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102); WREG32 1313 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702); WREG32 1314 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702); WREG32 1315 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602); WREG32 1316 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402); WREG32 1317 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202); WREG32 1318 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102); WREG32 1319 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401); WREG32 1320 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401); WREG32 1321 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401); WREG32 1322 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401); WREG32 1323 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401); WREG32 1324 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401); WREG32 1325 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101); WREG32 1326 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101); WREG32 1327 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101); WREG32 1328 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101); WREG32 1329 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101); WREG32 1330 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107); WREG32 1331 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107); WREG32 1332 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101); WREG32 1333 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101); WREG32 1334 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101); WREG32 1335 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101); WREG32 1336 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101); WREG32 1337 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501); WREG32 1338 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501); WREG32 1339 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301); WREG32 1340 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401); WREG32 1341 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101); WREG32 1342 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101); WREG32 1343 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101); WREG32 1344 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101); WREG32 1345 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101); WREG32 1346 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101); WREG32 1347 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101); WREG32 1348 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101); WREG32 1350 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101); WREG32 1351 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101); WREG32 1352 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101); WREG32 1353 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102); WREG32 1354 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101); WREG32 1355 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202); WREG32 1356 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201); WREG32 1357 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201); WREG32 1358 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202); WREG32 1359 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101); WREG32 1360 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101); WREG32 1361 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101); WREG32 1363 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101); WREG32 1364 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101); WREG32 1365 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201); WREG32 1366 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102); WREG32 1367 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101); WREG32 1368 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202); WREG32 1369 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201); WREG32 1370 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201); WREG32 1371 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202); WREG32 1372 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101); WREG32 1373 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101); WREG32 1374 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101); WREG32 1376 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101); WREG32 1377 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101); WREG32 1378 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301); WREG32 1379 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102); WREG32 1380 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101); WREG32 1381 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301); WREG32 1382 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201); WREG32 1383 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201); WREG32 1384 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402); WREG32 1385 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101); WREG32 1386 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101); WREG32 1387 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401); WREG32 1389 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101); WREG32 1390 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101); WREG32 1391 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401); WREG32 1392 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102); WREG32 1393 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101); WREG32 1394 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702); WREG32 1395 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201); WREG32 1396 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201); WREG32 1397 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602); WREG32 1398 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101); WREG32 1399 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101); WREG32 1400 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301); WREG32 1402 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101); WREG32 1403 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101); WREG32 1404 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501); WREG32 1405 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102); WREG32 1406 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101); WREG32 1407 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602); WREG32 1408 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201); WREG32 1409 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201); WREG32 1410 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702); WREG32 1411 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101); WREG32 1412 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101); WREG32 1413 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501); WREG32 1415 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101); WREG32 1416 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101); WREG32 1417 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601); WREG32 1418 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101); WREG32 1419 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101); WREG32 1420 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702); WREG32 1421 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101); WREG32 1422 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101); WREG32 1423 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702); WREG32 1424 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101); WREG32 1425 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101); WREG32 1426 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501); WREG32 1429 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1430 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1431 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1432 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1433 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1434 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1436 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1437 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1438 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1439 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1440 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1441 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1442 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1443 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1445 drivers/misc/habanalabs/goya/goya.c WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1446 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7); WREG32 1450 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_SCRAMB_EN + offset, WREG32 1452 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset, WREG32 1461 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask); WREG32 1463 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_NRTR_SCRAMB_EN + offset, WREG32 1465 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset, WREG32 1469 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT); WREG32 1470 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_NRTR_NON_LIN_SCRAMB, WREG32 1473 drivers/misc/habanalabs/goya/goya.c WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT); WREG32 1474 drivers/misc/habanalabs/goya/goya.c WREG32(mmPCI_NRTR_NON_LIN_SCRAMB, WREG32 1484 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0); WREG32 1486 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020); WREG32 1511 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr)); WREG32 1512 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr)); WREG32 1513 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH)); WREG32 1514 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_PQ_PI, 0); WREG32 1515 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_PQ_CI, 0); WREG32 1516 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0); WREG32 1517 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4); WREG32 1518 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8); WREG32 1519 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC); WREG32 1521 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo); WREG32 1522 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi); WREG32 1523 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo); WREG32 1524 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi); WREG32 1527 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_CQ_CFG1, 0x00080008); WREG32 1529 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo); WREG32 1530 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi); WREG32 1532 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM); WREG32 1534 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN); WREG32 1536 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT); WREG32 1538 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE); WREG32 1561 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo); WREG32 1562 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi); WREG32 1563 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo); WREG32 1564 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi); WREG32 1567 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014); WREG32 1569 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo); WREG32 1570 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi); WREG32 1572 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ); WREG32 1574 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN); WREG32 1576 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT); WREG32 1578 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE); WREG32 1592 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo); WREG32 1593 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi); WREG32 1621 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr)); WREG32 1622 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr)); WREG32 1623 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH)); WREG32 1624 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_PI + reg_off, 0); WREG32 1625 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_PQ_CI + reg_off, 0); WREG32 1626 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0); WREG32 1627 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4); WREG32 1628 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8); WREG32 1629 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC); WREG32 1631 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); WREG32 1632 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); WREG32 1633 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); WREG32 1634 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); WREG32 1636 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008); WREG32 1638 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); WREG32 1639 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); WREG32 1641 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off, WREG32 1644 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN); WREG32 1646 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT); WREG32 1648 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE); WREG32 1668 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo); WREG32 1669 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi); WREG32 1670 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo); WREG32 1671 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi); WREG32 1673 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014); WREG32 1675 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo); WREG32 1676 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi); WREG32 1678 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off, WREG32 1681 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN); WREG32 1683 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT); WREG32 1685 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE); WREG32 1703 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off, WREG32 1705 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off, WREG32 1737 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_QM_GLBL_CFG0, 0); WREG32 1738 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_CMDQ_GLBL_CFG0, 0); WREG32 1744 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_QM_GLBL_CFG0, 0); WREG32 1745 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0); WREG32 1747 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_QM_GLBL_CFG0, 0); WREG32 1748 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0); WREG32 1750 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_QM_GLBL_CFG0, 0); WREG32 1751 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0); WREG32 1753 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_QM_GLBL_CFG0, 0); WREG32 1754 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0); WREG32 1756 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_QM_GLBL_CFG0, 0); WREG32 1757 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0); WREG32 1759 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_QM_GLBL_CFG0, 0); WREG32 1760 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0); WREG32 1762 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_QM_GLBL_CFG0, 0); WREG32 1763 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0); WREG32 1765 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC7_QM_GLBL_CFG0, 0); WREG32 1766 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0); WREG32 1985 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT); WREG32 1986 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT); WREG32 1987 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT); WREG32 1988 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT); WREG32 1989 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT); WREG32 1999 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); WREG32 2000 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT); WREG32 2001 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT); WREG32 2002 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT); WREG32 2003 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT); WREG32 2004 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT); WREG32 2005 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT); WREG32 2006 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT); WREG32 2016 drivers/misc/habanalabs/goya/goya.c WREG32(mmMME_STALL, 0xFFFFFFFF); WREG32 2110 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); WREG32 2113 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0); WREG32 2114 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0); WREG32 2117 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1); WREG32 2123 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); WREG32 2146 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE); WREG32 2147 drivers/misc/habanalabs/goya/goya.c WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, WREG32 2223 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, CPU_RESET_ASSERT); WREG32 2228 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, CA53_RESET); WREG32 2230 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, unit_rst_val); WREG32 2241 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY); WREG32 2242 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_WARM_REBOOT, CPU_BOOT_STATUS_NA); WREG32 2244 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_CA53_CFG_RST_ADDR_LSB_0, WREG32 2246 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_CA53_CFG_RST_ADDR_MSB_0, WREG32 2250 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, WREG32 2398 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY); WREG32 2415 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_NA); WREG32 2438 drivers/misc/habanalabs/goya/goya.c WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT); WREG32 2439 drivers/misc/habanalabs/goya/goya.c WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT); WREG32 2440 drivers/misc/habanalabs/goya/goya.c WREG32(MMU_ASID_BUSY, 0x80000000 | asid); WREG32 2490 drivers/misc/habanalabs/goya/goya.c WREG32(mmSTLB_CACHE_INV_BASE_39_8, WREG32 2492 drivers/misc/habanalabs/goya/goya.c WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40); WREG32 2500 drivers/misc/habanalabs/goya/goya.c WREG32(mmMMU_MMU_ENABLE, 1); WREG32 2501 drivers/misc/habanalabs/goya/goya.c WREG32(mmMMU_SPI_MASK, 0xF); WREG32 2533 drivers/misc/habanalabs/goya/goya.c WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY); WREG32 2610 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL); WREG32 2615 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET); WREG32 2637 drivers/misc/habanalabs/goya/goya.c WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, WREG32 2643 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, WREG32 2646 drivers/misc/habanalabs/goya/goya.c WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM, WREG32 2788 drivers/misc/habanalabs/goya/goya.c WREG32(db_reg_offset, db_value); WREG32 2791 drivers/misc/habanalabs/goya/goya.c WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, WREG32 4015 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_EQ_CI, val); WREG32 4034 drivers/misc/habanalabs/goya/goya.c WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0); WREG32 4037 drivers/misc/habanalabs/goya/goya.c WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0); WREG32 4122 drivers/misc/habanalabs/goya/goya.c WREG32(addr - CFG_BASE, val); WREG32 4368 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0); WREG32 4373 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0); WREG32 4378 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0); WREG32 4383 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0); WREG32 4404 drivers/misc/habanalabs/goya/goya.c WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0); WREG32 4698 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr)); WREG32 4703 drivers/misc/habanalabs/goya/goya.c WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id, WREG32 4707 drivers/misc/habanalabs/goya/goya.c WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020); WREG32 4790 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF); WREG32 4791 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF); WREG32 4831 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_IF_ARUSER_OVR_EN, 0); WREG32 4832 drivers/misc/habanalabs/goya/goya.c WREG32(mmCPU_IF_AWUSER_OVR_EN, 0); WREG32 4898 drivers/misc/habanalabs/goya/goya.c WREG32(mmSTLB_INV_ALL_START, 1); WREG32 4947 drivers/misc/habanalabs/goya/goya.c WREG32(mmSTLB_CACHE_INV, WREG32 243 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); WREG32 251 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE80, 0x80004); WREG32 252 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD64, 7); WREG32 253 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD60, 0); WREG32 254 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); WREG32 255 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); WREG32 256 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD60, 1); WREG32 257 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); WREG32 258 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask)); WREG32 259 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE70, 0x10); WREG32 260 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE60, 0); WREG32 261 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE64, 0x420000); WREG32 262 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE00, 0xFFFFFFFF); WREG32 263 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE20, 0xFFFFFFFF); WREG32 264 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xEF4, input->id); WREG32 265 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xDF4, 0x80); WREG32 266 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE8C, input->frequency); WREG32 267 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE90, 0x7FF); WREG32 268 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE80, 0x7 | (input->id << 16)); WREG32 270 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE80, 4); WREG32 271 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD64, 0); WREG32 272 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD60, 1); WREG32 273 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD00, 0); WREG32 274 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD20, 0); WREG32 275 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xD60, 0); WREG32 276 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE20, 0); WREG32 277 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE00, 0); WREG32 278 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xDF4, 0x80); WREG32 279 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE70, 0); WREG32 280 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE60, 0); WREG32 281 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE64, 0); WREG32 282 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE8C, 0); WREG32 292 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE80, 4); WREG32 313 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); WREG32 317 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, val); WREG32 319 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, val); WREG32 337 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x20, 0); WREG32 345 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x34, 0x3FFC); WREG32 346 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x28, input->sink_mode); WREG32 347 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, 0x4001); WREG32 348 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x308, 0xA); WREG32 349 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x20, 1); WREG32 351 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x34, 0); WREG32 352 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x28, 0); WREG32 353 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, 0); WREG32 384 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); WREG32 388 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, val); WREG32 390 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, val); WREG32 406 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x20, 0); WREG32 426 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x34, 0x3FFC); WREG32 427 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x4, input->buffer_size); WREG32 428 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x28, input->sink_mode); WREG32 429 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x110, 0x700); WREG32 430 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x118, WREG32 432 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x11C, WREG32 434 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, 3); WREG32 435 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x308, 0xA); WREG32 436 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x20, 1); WREG32 438 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x34, 0); WREG32 439 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x4, 0x400); WREG32 440 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x118, 0); WREG32 441 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x11C, 0); WREG32 442 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x308, 0); WREG32 443 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x28, 0); WREG32 444 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, 0); WREG32 475 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); WREG32 477 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg, params->enable ? 0x33F : 0); WREG32 496 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x104, 1); WREG32 504 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0)); WREG32 505 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0)); WREG32 506 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0)); WREG32 507 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0)); WREG32 508 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1)); WREG32 509 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1)); WREG32 510 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1)); WREG32 511 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1)); WREG32 512 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x224, 0); WREG32 513 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x234, 0); WREG32 514 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x30C, input->bw_win); WREG32 515 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x308, input->win_capture); WREG32 524 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x700, pcie_base | 0xB00 | (input->id << 12)); WREG32 525 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x708, pcie_base | 0xA00 | (input->id << 12)); WREG32 526 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x70C, pcie_base | 0xC00 | (input->id << 12)); WREG32 528 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x100, 0x11); WREG32 529 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, 0x1); WREG32 531 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x200, 0); WREG32 532 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x204, 0); WREG32 533 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x208, 0xFFFFFFFF); WREG32 534 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x20C, 0xFFFFFFFF); WREG32 535 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x240, 0); WREG32 536 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x244, 0); WREG32 537 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x248, 0xFFFFFFFF); WREG32 538 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x24C, 0xFFFFFFFF); WREG32 539 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x224, 0xFFFFFFFF); WREG32 540 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x234, 0x1070F); WREG32 541 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x30C, 0); WREG32 542 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x308, 0xFFFF); WREG32 543 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x700, 0xA000B00); WREG32 544 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x708, 0xA000A00); WREG32 545 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x70C, 0xA000C00); WREG32 546 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x100, 1); WREG32 547 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x304, 0); WREG32 548 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0x104, 0); WREG32 591 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE04, 0x41013046); WREG32 592 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE04, 0x41013040); WREG32 595 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4, WREG32 598 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE04, 0x41013041); WREG32 599 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xC00, 0x8000003F); WREG32 622 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xE04, 0x41013040); WREG32 633 drivers/misc/habanalabs/goya/goya_coresight.c WREG32(base_reg + 0xCC0, 0); WREG32 23 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr, 0); WREG32 81 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 104 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 128 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 160 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 180 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 194 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 210 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 228 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 251 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 262 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 269 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 303 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 335 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 355 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 381 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 413 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 433 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 459 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 491 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 511 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 537 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 569 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 589 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 615 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 647 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 667 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 689 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 704 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 711 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 729 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 753 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 785 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 805 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 821 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 839 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 861 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 872 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 886 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 893 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 911 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 935 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 967 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 987 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1003 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1021 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1043 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1054 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1068 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1075 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1093 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1117 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1149 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1169 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1185 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1203 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1225 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1236 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1250 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1257 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1275 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1299 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1331 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1351 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1367 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1385 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1407 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1418 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1432 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1439 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1457 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1481 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1513 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1533 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1549 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1567 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1589 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1600 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1614 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1621 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1639 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1663 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1695 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1715 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1731 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1749 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1771 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1782 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1796 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1803 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1821 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1845 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1877 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1897 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1913 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1931 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1953 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1964 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1978 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 1985 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 2003 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 2027 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 2059 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 2079 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 2095 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 2113 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 2135 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 2146 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); WREG32 2266 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, mask); WREG32 2333 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_HIT_BLOCK, 0xFFFF); WREG32 2334 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_HBW_RANGE_HIT_BLOCK, 0xFF); WREG32 2337 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_HBW_RANGE_HIT_BLOCK, 0xFE); WREG32 2340 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_HBW_RANGE_BASE_31_0_0, 0); WREG32 2341 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_HBW_RANGE_BASE_49_32_0, 0); WREG32 2342 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_HBW_RANGE_MASK_31_0_0, 0); WREG32 2343 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_HBW_RANGE_MASK_49_32_0, 0xFFF80); WREG32 2351 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_HBW_RANGE_BASE_31_0_1, dram_addr_lo); WREG32 2352 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_HBW_RANGE_BASE_49_32_1, dram_addr_hi); WREG32 2353 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_HBW_RANGE_MASK_31_0_1, 0xE0000000); WREG32 2354 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_HBW_RANGE_MASK_49_32_1, 0x3FFFF); WREG32 2358 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2359 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2360 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2361 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2362 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2363 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2364 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2365 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2366 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2367 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2368 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2369 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2370 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2371 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2372 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2373 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2374 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2375 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2376 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2377 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2378 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2379 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2380 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2381 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2382 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2383 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2384 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2385 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmDMA_MACRO_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2387 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2388 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2389 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2390 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2391 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2392 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2394 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2395 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2396 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2397 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2398 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2399 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2402 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2403 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2404 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2405 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2407 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2408 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2409 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2410 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2412 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2413 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2414 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2415 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2417 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2418 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2419 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2420 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2422 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2423 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2424 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2425 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2427 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2428 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2429 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2430 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2437 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2438 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2439 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2440 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2442 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2443 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2444 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2445 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2447 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2448 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2449 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2450 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2452 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2453 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2454 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2455 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2457 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2458 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2459 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2460 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2462 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2463 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2464 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2465 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2467 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2468 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2469 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2470 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2471 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2472 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2473 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2474 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2475 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2476 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2477 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2478 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2479 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2480 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2481 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2482 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2483 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2484 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2485 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2486 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2487 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2488 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2489 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2490 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2491 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2492 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2493 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2494 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME1_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2496 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2497 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2498 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2499 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2500 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2501 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2502 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2503 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2504 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2505 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2506 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2507 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2508 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2509 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2510 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2511 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2512 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2513 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2514 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2515 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2516 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2517 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2518 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2519 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2520 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2521 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2522 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2523 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME2_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2525 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2526 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2527 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2528 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2529 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2530 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2531 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2532 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2533 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2534 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2535 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2536 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2537 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2538 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2539 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2540 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2541 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2542 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2543 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2544 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2545 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2546 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2547 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2548 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2549 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2550 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2551 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2552 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME3_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2554 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2555 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2556 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2557 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2558 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2559 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2560 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2561 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2562 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2563 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2564 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2565 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2566 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2567 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2568 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2569 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2570 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2571 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2572 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2573 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2574 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2575 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2576 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2577 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2578 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2579 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2580 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2581 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME4_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2583 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2584 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2585 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2586 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2587 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2588 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2589 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2590 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2591 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2592 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2593 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2594 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2595 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2596 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2597 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2598 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2599 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2600 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2601 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2602 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2603 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2604 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2605 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2606 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2607 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2608 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2609 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2610 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME5_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2612 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2613 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2614 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2615 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2616 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2617 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2618 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2619 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2620 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2621 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2622 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2623 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2624 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2625 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2626 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2627 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2628 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2629 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2630 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2631 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2632 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2633 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2634 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2635 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2636 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2637 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2638 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2639 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmMME6_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2641 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2642 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_HBW_RANGE_HIT, 0xFE); WREG32 2645 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_L_0, 0); WREG32 2646 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_H_0, 0); WREG32 2647 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_L_0, 0); WREG32 2648 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2655 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2656 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2657 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2658 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2660 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2661 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2662 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2663 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2664 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2665 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2666 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2667 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2668 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2669 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2670 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2671 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2672 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2673 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2674 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2675 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2676 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2677 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2678 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2679 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2680 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2681 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2682 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2683 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2684 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2685 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2686 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2687 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2689 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2690 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2693 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2694 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2695 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2696 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2703 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2704 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2705 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2706 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2708 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2709 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2710 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2711 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2712 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2713 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2714 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2715 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2716 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2717 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2718 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2719 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2720 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2721 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2722 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2723 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2724 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2725 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2726 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2727 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2728 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2729 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2730 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2731 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2732 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2733 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2734 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2735 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC1_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2737 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2738 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2741 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2742 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2743 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2744 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2751 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2752 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2753 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2754 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2756 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2757 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2758 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2759 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2760 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2761 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2762 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2763 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2764 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2765 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2766 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2767 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2768 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2769 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2770 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2771 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2772 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2773 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2774 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2775 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2776 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2777 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2778 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2779 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2780 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2781 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2782 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2783 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC2_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2785 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2786 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2789 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2790 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2791 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2792 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2799 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2800 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2801 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2802 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2804 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2805 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2806 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2807 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2808 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2809 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2810 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2811 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2812 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2813 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2814 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2815 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2816 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2817 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2818 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2819 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2820 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2821 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2822 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2823 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2824 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2825 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2826 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2827 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2828 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2829 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2830 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2831 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC3_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2833 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2834 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2837 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2838 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2839 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2840 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2847 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2848 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2849 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2850 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2852 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2853 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2854 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2855 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2856 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2857 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2858 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2859 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2860 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2861 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2862 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2863 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2864 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2865 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2866 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2867 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2868 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2869 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2870 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2871 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2872 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2873 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2874 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2875 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2876 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2877 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2878 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2879 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC4_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2881 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2882 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2885 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2886 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2887 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2888 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2895 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2896 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2897 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2898 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2900 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2901 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2902 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2903 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2904 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2905 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2906 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2907 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2908 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2909 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2910 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2911 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2912 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2913 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2914 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2915 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2916 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2917 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2918 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2919 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2920 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2921 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2922 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2923 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2924 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2925 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2926 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2927 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC5_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2929 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2930 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_HBW_RANGE_HIT, 0xFE); WREG32 2933 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_HBW_RANGE_BASE_L_0, 0); WREG32 2934 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_HBW_RANGE_BASE_H_0, 0); WREG32 2935 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_HBW_RANGE_MASK_L_0, 0); WREG32 2936 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2943 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2944 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2945 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2946 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2948 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2949 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2950 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2951 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 2952 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 2953 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 2954 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 2955 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 2956 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 2957 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 2958 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 2959 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 2960 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 2961 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 2962 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 2963 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 2964 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 2965 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 2966 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 2967 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 2968 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 2969 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 2970 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 2971 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 2972 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 2973 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 2974 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 2975 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC6_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 2977 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_HIT, 0xFFFF); WREG32 2978 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_HBW_RANGE_HIT, 0xFE); WREG32 2981 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_L_0, 0); WREG32 2982 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_H_0, 0); WREG32 2983 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_L_0, 0); WREG32 2984 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_H_0, 0xFFF80); WREG32 2991 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_L_1, dram_addr_lo); WREG32 2992 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_H_1, dram_addr_hi); WREG32 2993 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_L_1, 0xE0000000); WREG32 2994 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_H_1, 0x3FFFF); WREG32 2996 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_0, lbw_rng0_base); WREG32 2997 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_0, lbw_rng0_mask); WREG32 2998 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_1, lbw_rng1_base); WREG32 2999 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_1, lbw_rng1_mask); WREG32 3000 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_2, lbw_rng2_base); WREG32 3001 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_2, lbw_rng2_mask); WREG32 3002 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_3, lbw_rng3_base); WREG32 3003 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_3, lbw_rng3_mask); WREG32 3004 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_4, lbw_rng4_base); WREG32 3005 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_4, lbw_rng4_mask); WREG32 3006 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_5, lbw_rng5_base); WREG32 3007 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_5, lbw_rng5_mask); WREG32 3008 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_6, lbw_rng6_base); WREG32 3009 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask); WREG32 3010 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_7, lbw_rng7_base); WREG32 3011 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_7, lbw_rng7_mask); WREG32 3012 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_8, lbw_rng8_base); WREG32 3013 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_8, lbw_rng8_mask); WREG32 3014 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_9, lbw_rng9_base); WREG32 3015 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_9, lbw_rng9_mask); WREG32 3016 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_10, lbw_rng10_base); WREG32 3017 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_10, lbw_rng10_mask); WREG32 3018 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_11, lbw_rng11_base); WREG32 3019 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_11, lbw_rng11_mask); WREG32 3020 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_12, lbw_rng12_base); WREG32 3021 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_12, lbw_rng12_mask); WREG32 3022 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_13, lbw_rng13_base); WREG32 3023 drivers/misc/habanalabs/goya/goya_security.c WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_13, lbw_rng13_mask); WREG32 1044 drivers/misc/habanalabs/habanalabs.h WREG32(reg, tmp_); \ WREG32 1052 drivers/misc/habanalabs/habanalabs.h WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | \