WR 114 drivers/block/paride/bpck.c case 0: WR(4,0x40); WR 117 drivers/block/paride/bpck.c WR(4,0); WR 120 drivers/block/paride/bpck.c case 1: WR(4,0x50); WR 123 drivers/block/paride/bpck.c WR(4,0x10); WR 126 drivers/block/paride/bpck.c case 2: WR(4,0x48); WR 130 drivers/block/paride/bpck.c WR(4,8); WR 133 drivers/block/paride/bpck.c case 3: WR(4,0x48); WR 137 drivers/block/paride/bpck.c WR(4,8); WR 140 drivers/block/paride/bpck.c case 4: WR(4,0x48); WR 144 drivers/block/paride/bpck.c WR(4,8); WR 155 drivers/block/paride/bpck.c case 0: WR(4,0x40); WR 162 drivers/block/paride/bpck.c WR(4,0); WR 165 drivers/block/paride/bpck.c case 1: WR(4,0x50); WR 169 drivers/block/paride/bpck.c WR(4,0x10); WR 172 drivers/block/paride/bpck.c case 2: WR(4,0x48); WR 176 drivers/block/paride/bpck.c WR(4,8); WR 179 drivers/block/paride/bpck.c case 3: WR(4,0x48); WR 183 drivers/block/paride/bpck.c WR(4,8); WR 186 drivers/block/paride/bpck.c case 4: WR(4,0x48); WR 190 drivers/block/paride/bpck.c WR(4,8); WR 228 drivers/block/paride/bpck.c case 0: t2(8); WR(4,0); WR 231 drivers/block/paride/bpck.c case 1: t2(8); WR(4,0x10); WR 236 drivers/block/paride/bpck.c case 4: w2(0); WR(4,8); WR 241 drivers/block/paride/bpck.c WR(5,8); WR 244 drivers/block/paride/bpck.c WR(0x46,0x10); /* fiddle with ESS logic ??? */ WR 245 drivers/block/paride/bpck.c WR(0x4c,0x38); WR 246 drivers/block/paride/bpck.c WR(0x4d,0x88); WR 247 drivers/block/paride/bpck.c WR(0x46,0xa0); WR 248 drivers/block/paride/bpck.c WR(0x41,0); WR 249 drivers/block/paride/bpck.c WR(0x4e,8); WR 288 drivers/block/paride/bpck.c WR(0x13,0x7f); WR 299 drivers/block/paride/bpck.c WR(0x13,0x7f); WR 311 drivers/block/paride/bpck.c WR(7,3); WR 312 drivers/block/paride/bpck.c WR(4,8); WR 329 drivers/block/paride/bpck.c WR(7,0); WR 359 drivers/block/paride/bpck.c WR(4,0); WR 361 drivers/block/paride/bpck.c WR(6,8); WR 362 drivers/block/paride/bpck.c WR(6,0xc); WR 366 drivers/block/paride/bpck.c WR(6,f+0xc); WR 367 drivers/block/paride/bpck.c WR(6,f+0xd); WR 368 drivers/block/paride/bpck.c WR(6,f+0xc); WR 374 drivers/block/paride/bpck.c WR(6,0xc); WR 375 drivers/block/paride/bpck.c WR(6,0xd); WR 376 drivers/block/paride/bpck.c WR(6,0xc); WR 383 drivers/block/paride/bpck.c WR(6,8); WR 384 drivers/block/paride/bpck.c WR(6,0); WR 385 drivers/block/paride/bpck.c WR(5,8); WR 391 drivers/block/paride/bpck.c WR(7,3); WR 392 drivers/block/paride/bpck.c WR(4,8); WR 224 drivers/block/paride/epat.c WR(0x8,0x12);WR(0xc,0x14);WR(0x12,0x10); WR 225 drivers/block/paride/epat.c WR(0xe,0xf);WR(0xf,4); WR 227 drivers/block/paride/epat.c WR(0xe,0xd);WR(0xf,0); WR 241 drivers/block/paride/epat.c WR(8,0x10); WR(0xc,0x14); WR(0xa,0x38); WR(0x12,0x10); WR 273 drivers/block/paride/epat.c WR(0x13,1); WR(0x13,0); WR(0xa,0x11); WR 297 drivers/block/paride/epat.c WR(0xa,0x38); /* read the version code */ WR 124 drivers/block/paride/epia.c WR(0x86,8); WR 175 drivers/block/paride/epia.c case 3: if (count > 512) WR(0x84,3); WR 178 drivers/block/paride/epia.c w2(4); WR(0x84,0); WR 181 drivers/block/paride/epia.c case 4: if (count > 512) WR(0x84,3); WR 184 drivers/block/paride/epia.c w2(4); WR(0x84,0); WR 187 drivers/block/paride/epia.c case 5: if (count > 512) WR(0x84,3); WR 190 drivers/block/paride/epia.c w2(4); WR(0x84,0); WR 215 drivers/block/paride/epia.c case 3: if (count < 512) WR(0x84,1); WR 218 drivers/block/paride/epia.c if (count < 512) WR(0x84,0); WR 221 drivers/block/paride/epia.c case 4: if (count < 512) WR(0x84,1); WR 224 drivers/block/paride/epia.c if (count < 512) WR(0x84,0); WR 227 drivers/block/paride/epia.c case 5: if (count < 512) WR(0x84,1); WR 230 drivers/block/paride/epia.c if (count < 512) WR(0x84,0); WR 244 drivers/block/paride/epia.c WR(6,0xa0+j*0x10); WR 246 drivers/block/paride/epia.c WR(2,k^0xaa); WR 247 drivers/block/paride/epia.c WR(3,k^0x55); WR 250 drivers/block/paride/epia.c WR(2,1); WR(3,1); WR 256 drivers/block/paride/epia.c WR(0x84,8); WR 262 drivers/block/paride/epia.c WR(0x84,0); WR 73 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; WR 79 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c WR = ram->next->bios.timing_10_WR; WR 87 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; WR 103 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c WR = ramxlat(ramgddr3_wr_lo, WR); WR 104 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) WR 115 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c ram->mr[1] |= (WR & 0x03) << 4; WR 116 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c ram->mr[1] |= (WR & 0x04) << 5; WR 38 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c int WL, CL, WR, at[2], dt, ds; WR 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; WR 70 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) WR 73 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c WR -= 4; WR 76 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c ram->mr[0] |= (WR & 0x0f) << 8; WR 118 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c ram->mr[8] |= (WR & 0x10) >> 3; WR 375 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c timing[1] = (T(WR) + 1 + T(CWL)) << 24 | WR 110 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c timing[1] = (T(WR) + 1 + T(CWL)) << 24 | WR 177 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); WR 63 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c int CL, WR, DLL = 0, ODT = 0; WR 68 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c WR = ram->next->bios.timing_10_WR; WR 74 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; WR 87 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c WR = ramxlat(ramddr2_wr, WR); WR 88 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c if (CL < 0 || WR < 0) WR 92 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c ram->mr[0] |= (WR & 0x07) << 9; WR 72 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c int CWL, CL, WR, DLL = 0, ODT = 0; WR 84 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c WR = ram->next->bios.timing_10_WR; WR 90 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; WR 102 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c WR = ramxlat(ramddr3_wr, WR); WR 103 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c if (CL < 0 || CWL < 0 || WR < 0) WR 107 drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c ram->mr[0] |= (WR & 0x07) << 9; WR 105 drivers/i2c/busses/i2c-au1550.c WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR); WR 108 drivers/i2c/busses/i2c-au1550.c WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC); WR 124 drivers/i2c/busses/i2c-au1550.c WR(adap, PSC_SMBTXRX, addr); WR 125 drivers/i2c/busses/i2c-au1550.c WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS); WR 169 drivers/i2c/busses/i2c-au1550.c WR(adap, PSC_SMBTXRX, 0); WR 177 drivers/i2c/busses/i2c-au1550.c WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP); WR 197 drivers/i2c/busses/i2c-au1550.c WR(adap, PSC_SMBTXRX, data); WR 206 drivers/i2c/busses/i2c-au1550.c WR(adap, PSC_SMBTXRX, data); WR 219 drivers/i2c/busses/i2c-au1550.c WR(adap, PSC_CTRL, PSC_CTRL_ENABLE); WR 238 drivers/i2c/busses/i2c-au1550.c WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND); WR 257 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); WR 258 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE); WR 259 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_SMBCFG, 0); WR 260 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_CTRL, PSC_CTRL_ENABLE); WR 265 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_SMBCFG, cfg); WR 271 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_SMBCFG, cfg); WR 272 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK); WR 277 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(20) | \ WR 283 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_SMBCFG, cfg); WR 287 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND); WR 292 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_SMBCFG, 0); WR 293 drivers/i2c/busses/i2c-au1550.c WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); WR 228 include/linux/ceph/rados.h f(WRITE, __CEPH_OSD_OP(WR, DATA, 1), "write") \ WR 229 include/linux/ceph/rados.h f(WRITEFULL, __CEPH_OSD_OP(WR, DATA, 2), "writefull") \ WR 230 include/linux/ceph/rados.h f(TRUNCATE, __CEPH_OSD_OP(WR, DATA, 3), "truncate") \ WR 231 include/linux/ceph/rados.h f(ZERO, __CEPH_OSD_OP(WR, DATA, 4), "zero") \ WR 232 include/linux/ceph/rados.h f(DELETE, __CEPH_OSD_OP(WR, DATA, 5), "delete") \ WR 235 include/linux/ceph/rados.h f(APPEND, __CEPH_OSD_OP(WR, DATA, 6), "append") \ WR 236 include/linux/ceph/rados.h f(SETTRUNC, __CEPH_OSD_OP(WR, DATA, 8), "settrunc") \ WR 237 include/linux/ceph/rados.h f(TRIMTRUNC, __CEPH_OSD_OP(WR, DATA, 9), "trimtrunc") \ WR 240 include/linux/ceph/rados.h f(TMAPPUT, __CEPH_OSD_OP(WR, DATA, 11), "tmapput") \ WR 243 include/linux/ceph/rados.h f(CREATE, __CEPH_OSD_OP(WR, DATA, 13), "create") \ WR 244 include/linux/ceph/rados.h f(ROLLBACK, __CEPH_OSD_OP(WR, DATA, 14), "rollback") \ WR 246 include/linux/ceph/rados.h f(WATCH, __CEPH_OSD_OP(WR, DATA, 15), "watch") \ WR 253 include/linux/ceph/rados.h f(OMAPSETVALS, __CEPH_OSD_OP(WR, DATA, 21), "omap-set-vals") \ WR 254 include/linux/ceph/rados.h f(OMAPSETHEADER, __CEPH_OSD_OP(WR, DATA, 22), "omap-set-header") \ WR 255 include/linux/ceph/rados.h f(OMAPCLEAR, __CEPH_OSD_OP(WR, DATA, 23), "omap-clear") \ WR 256 include/linux/ceph/rados.h f(OMAPRMKEYS, __CEPH_OSD_OP(WR, DATA, 24), "omap-rm-keys") \ WR 260 include/linux/ceph/rados.h f(COPY_FROM, __CEPH_OSD_OP(WR, DATA, 26), "copy-from") \ WR 262 include/linux/ceph/rados.h f(UNDIRTY, __CEPH_OSD_OP(WR, DATA, 28), "undirty") \ WR 273 include/linux/ceph/rados.h f(SETALLOCHINT, __CEPH_OSD_OP(WR, DATA, 35), "set-alloc-hint") \ WR 276 include/linux/ceph/rados.h f(CLONERANGE, __CEPH_OSD_OP(WR, MULTI, 1), "clonerange") \ WR 287 include/linux/ceph/rados.h f(SETXATTR, __CEPH_OSD_OP(WR, ATTR, 1), "setxattr") \ WR 288 include/linux/ceph/rados.h f(SETXATTRS, __CEPH_OSD_OP(WR, ATTR, 2), "setxattrs") \ WR 289 include/linux/ceph/rados.h f(RESETXATTRS, __CEPH_OSD_OP(WR, ATTR, 3), "resetxattrs") \ WR 290 include/linux/ceph/rados.h f(RMXATTR, __CEPH_OSD_OP(WR, ATTR, 4), "rmxattr") \ WR 304 include/linux/ceph/rados.h f(WRLOCK, __CEPH_OSD_OP(WR, LOCK, 1), "wrlock") \ WR 305 include/linux/ceph/rados.h f(WRUNLOCK, __CEPH_OSD_OP(WR, LOCK, 2), "wrunlock") \ WR 306 include/linux/ceph/rados.h f(RDLOCK, __CEPH_OSD_OP(WR, LOCK, 3), "rdlock") \ WR 307 include/linux/ceph/rados.h f(RDUNLOCK, __CEPH_OSD_OP(WR, LOCK, 4), "rdunlock") \ WR 308 include/linux/ceph/rados.h f(UPLOCK, __CEPH_OSD_OP(WR, LOCK, 5), "uplock") \ WR 309 include/linux/ceph/rados.h f(DNLOCK, __CEPH_OSD_OP(WR, LOCK, 6), "dnlock") \ WR 103 sound/soc/au1x/ac97c.c WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ); WR 142 sound/soc/au1x/ac97c.c WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v)); WR 159 sound/soc/au1x/ac97c.c WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN); WR 161 sound/soc/au1x/ac97c.c WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG); WR 162 sound/soc/au1x/ac97c.c WR(ctx, AC97_CONFIG, ctx->cfg); WR 170 sound/soc/au1x/ac97c.c WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS); WR 172 sound/soc/au1x/ac97c.c WR(ctx, AC97_CONFIG, ctx->cfg); WR 267 sound/soc/au1x/ac97c.c WR(ctx, AC97_ENABLE, EN_D | EN_CE); WR 268 sound/soc/au1x/ac97c.c WR(ctx, AC97_ENABLE, EN_CE); WR 271 sound/soc/au1x/ac97c.c WR(ctx, AC97_CONFIG, ctx->cfg); WR 294 sound/soc/au1x/ac97c.c WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */ WR 306 sound/soc/au1x/ac97c.c WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */ WR 315 sound/soc/au1x/ac97c.c WR(ctx, AC97_ENABLE, EN_D | EN_CE); WR 316 sound/soc/au1x/ac97c.c WR(ctx, AC97_ENABLE, EN_CE); WR 317 sound/soc/au1x/ac97c.c WR(ctx, AC97_CONFIG, ctx->cfg); WR 146 sound/soc/au1x/i2sc.c WR(ctx, I2S_ENABLE, EN_D | EN_CE); WR 147 sound/soc/au1x/i2sc.c WR(ctx, I2S_ENABLE, EN_CE); WR 149 sound/soc/au1x/i2sc.c WR(ctx, I2S_CFG, ctx->cfg); WR 154 sound/soc/au1x/i2sc.c WR(ctx, I2S_CFG, ctx->cfg); WR 155 sound/soc/au1x/i2sc.c WR(ctx, I2S_ENABLE, EN_D); /* power off */ WR 278 sound/soc/au1x/i2sc.c WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */ WR 288 sound/soc/au1x/i2sc.c WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */