WB_ENABLE          78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
WB_ENABLE          91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
WB_ENABLE          54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(WB_ENABLE, CNV, inst),\
WB_ENABLE          87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
WB_ENABLE         151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	type WB_ENABLE;\
WB_ENABLE         217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	uint32_t WB_ENABLE;
WB_ENABLE         118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
WB_ENABLE         144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
WB_ENABLE         204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled);
WB_ENABLE          58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SRI2(WB_ENABLE, CNV, inst),\
WB_ENABLE         106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_ENABLE, WB_ENABLE, mask_sh),\
WB_ENABLE         230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	type WB_ENABLE;\
WB_ENABLE         358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	uint32_t WB_ENABLE;
WB_ENABLE        1139 drivers/media/platform/atmel/atmel-isc-base.c 				WB_ENABLE | GAM_ENABLES;
WB_ENABLE        1148 drivers/media/platform/atmel/atmel-isc-base.c 				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
WB_ENABLE        1158 drivers/media/platform/atmel/atmel-isc-base.c 				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
WB_ENABLE        1168 drivers/media/platform/atmel/atmel-isc-base.c 				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
WB_ENABLE        1178 drivers/media/platform/atmel/atmel-isc-base.c 				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |