WA_SET_BIT_MASKED 192 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); WA_SET_BIT_MASKED 195 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); WA_SET_BIT_MASKED 198 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, WA_SET_BIT_MASKED 207 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(HDC_CHICKEN0, WA_SET_BIT_MASKED 222 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); WA_SET_BIT_MASKED 245 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); WA_SET_BIT_MASKED 252 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, WA_SET_BIT_MASKED 255 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, WA_SET_BIT_MASKED 258 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(HDC_CHICKEN0, WA_SET_BIT_MASKED 271 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); WA_SET_BIT_MASKED 274 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); WA_SET_BIT_MASKED 288 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, WA_SET_BIT_MASKED 290 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, WA_SET_BIT_MASKED 296 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, WA_SET_BIT_MASKED 302 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, WA_SET_BIT_MASKED 308 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(CACHE_MODE_1, WA_SET_BIT_MASKED 317 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(HDC_CHICKEN0, WA_SET_BIT_MASKED 335 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(HDC_CHICKEN0, WA_SET_BIT_MASKED 340 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, WA_SET_BIT_MASKED 344 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); WA_SET_BIT_MASKED 367 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); WA_SET_BIT_MASKED 423 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, WA_SET_BIT_MASKED 427 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, WA_SET_BIT_MASKED 440 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, WA_SET_BIT_MASKED 444 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, WA_SET_BIT_MASKED 454 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, WA_SET_BIT_MASKED 464 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, WA_SET_BIT_MASKED 468 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, WA_SET_BIT_MASKED 478 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, WA_SET_BIT_MASKED 483 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5); WA_SET_BIT_MASKED 486 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, WA_SET_BIT_MASKED 491 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, WA_SET_BIT_MASKED 495 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); WA_SET_BIT_MASKED 498 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); WA_SET_BIT_MASKED 509 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT); WA_SET_BIT_MASKED 527 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, WA_SET_BIT_MASKED 537 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); WA_SET_BIT_MASKED 543 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, WA_SET_BIT_MASKED 548 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, WA_SET_BIT_MASKED 563 drivers/gpu/drm/i915/gt/intel_workarounds.c WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,