VceBootLevel 1560 drivers/gpu/drm/amd/amdgpu/kv_dpm.c offsetof(SMU7_Fusion_DpmTable, VceBootLevel), VceBootLevel 280 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint8_t VceBootLevel; VceBootLevel 264 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint8_t VceBootLevel; VceBootLevel 298 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint8_t VceBootLevel; VceBootLevel 304 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint8_t VceBootLevel; VceBootLevel 338 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint8_t VceBootLevel; VceBootLevel 241 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint8_t VceBootLevel; VceBootLevel 1567 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->VceBootLevel = 0; VceBootLevel 2011 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->VceBootLevel = 0; VceBootLevel 2905 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c VceBootLevel, 0); /* temp hard code to level 0, vce can set min evclk*/ VceBootLevel 1434 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c table->VceBootLevel = 0; VceBootLevel 2331 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c case VceBootLevel: VceBootLevel 2332 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c return offsetof(SMU73_Discrete_DpmTable, VceBootLevel); VceBootLevel 2409 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.VceBootLevel = VceBootLevel 2412 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.VceBootLevel = 0; VceBootLevel 2415 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c offsetof(SMU73_Discrete_DpmTable, VceBootLevel); VceBootLevel 2421 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; VceBootLevel 2428 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); VceBootLevel 1300 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->VceBootLevel = 0; VceBootLevel 2218 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.VceBootLevel = VceBootLevel 2221 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.VceBootLevel = 0; VceBootLevel 2224 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c offsetof(SMU74_Discrete_DpmTable, VceBootLevel); VceBootLevel 2230 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; VceBootLevel 2237 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); VceBootLevel 2346 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c case VceBootLevel: VceBootLevel 2347 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c return offsetof(SMU74_Discrete_DpmTable, VceBootLevel); VceBootLevel 1381 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->VceBootLevel = 0; VceBootLevel 2639 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c case VceBootLevel: VceBootLevel 2640 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c return offsetof(SMU72_Discrete_DpmTable, VceBootLevel); VceBootLevel 2718 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.VceBootLevel = VceBootLevel 2722 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c offsetof(SMU72_Discrete_DpmTable, VceBootLevel); VceBootLevel 2728 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; VceBootLevel 2736 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); VceBootLevel 372 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.VceBootLevel = VceBootLevel 375 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.VceBootLevel = 0; VceBootLevel 378 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c offsetof(SMU75_Discrete_DpmTable, VceBootLevel); VceBootLevel 384 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; VceBootLevel 391 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); VceBootLevel 1217 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->VceBootLevel = 0; VceBootLevel 2194 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c case VceBootLevel: VceBootLevel 2195 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c return offsetof(SMU75_Discrete_DpmTable, VceBootLevel); VceBootLevel 3623 drivers/gpu/drm/radeon/ci_dpm.c table->VceBootLevel = 0; VceBootLevel 4127 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); VceBootLevel 4130 drivers/gpu/drm/radeon/ci_dpm.c tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); VceBootLevel 1495 drivers/gpu/drm/radeon/kv_dpm.c offsetof(SMU7_Fusion_DpmTable, VceBootLevel), VceBootLevel 337 drivers/gpu/drm/radeon/smu7_discrete.h uint8_t VceBootLevel; VceBootLevel 241 drivers/gpu/drm/radeon/smu7_fusion.h uint8_t VceBootLevel;