VM_L2_CNTL        141 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
VM_L2_CNTL        142 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
VM_L2_CNTL        144 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
VM_L2_CNTL        146 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
VM_L2_CNTL        147 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
VM_L2_CNTL        148 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
VM_L2_CNTL        310 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 	WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
VM_L2_CNTL        608 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
VM_L2_CNTL        609 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
VM_L2_CNTL        610 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
VM_L2_CNTL        611 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
VM_L2_CNTL        612 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
VM_L2_CNTL        613 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
VM_L2_CNTL        614 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
VM_L2_CNTL        727 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
VM_L2_CNTL        835 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
VM_L2_CNTL        836 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
VM_L2_CNTL        837 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
VM_L2_CNTL        838 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
VM_L2_CNTL        839 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
VM_L2_CNTL        840 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
VM_L2_CNTL        841 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
VM_L2_CNTL        971 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
VM_L2_CNTL        170 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
VM_L2_CNTL        171 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
VM_L2_CNTL        173 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
VM_L2_CNTL        175 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
VM_L2_CNTL        176 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
VM_L2_CNTL        177 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
VM_L2_CNTL        357 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
VM_L2_CNTL       5453 drivers/gpu/drm/radeon/cik.c 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
VM_L2_CNTL       5570 drivers/gpu/drm/radeon/cik.c 	WREG32(VM_L2_CNTL,
VM_L2_CNTL       2410 drivers/gpu/drm/radeon/evergreen.c 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
VM_L2_CNTL       2464 drivers/gpu/drm/radeon/evergreen.c 	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
VM_L2_CNTL       2493 drivers/gpu/drm/radeon/evergreen.c 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
VM_L2_CNTL       1294 drivers/gpu/drm/radeon/ni.c 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
VM_L2_CNTL       1375 drivers/gpu/drm/radeon/ni.c 	WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
VM_L2_CNTL       1143 drivers/gpu/drm/radeon/r600.c 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
VM_L2_CNTL       1197 drivers/gpu/drm/radeon/r600.c 	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
VM_L2_CNTL       1235 drivers/gpu/drm/radeon/r600.c 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
VM_L2_CNTL        910 drivers/gpu/drm/radeon/rv770.c 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
VM_L2_CNTL        957 drivers/gpu/drm/radeon/rv770.c 	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
VM_L2_CNTL        987 drivers/gpu/drm/radeon/rv770.c 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
VM_L2_CNTL       4305 drivers/gpu/drm/radeon/si.c 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
VM_L2_CNTL       4393 drivers/gpu/drm/radeon/si.c 	WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |