VLV_DISPLAY_BASE  843 drivers/gpu/drm/i915/display/intel_gmbus.c 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
VLV_DISPLAY_BASE  484 drivers/gpu/drm/i915/i915_pci.c 	.display_mmio_offset = VLV_DISPLAY_BASE,
VLV_DISPLAY_BASE  578 drivers/gpu/drm/i915/i915_pci.c 	.display_mmio_offset = VLV_DISPLAY_BASE,
VLV_DISPLAY_BASE  205 drivers/gpu/drm/i915/i915_reg.h #define VLV_MIPI_BASE			VLV_DISPLAY_BASE
VLV_DISPLAY_BASE 1067 drivers/gpu/drm/i915/i915_reg.h #define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
VLV_DISPLAY_BASE 1089 drivers/gpu/drm/i915/i915_reg.h #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
VLV_DISPLAY_BASE 1090 drivers/gpu/drm/i915/i915_reg.h #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
VLV_DISPLAY_BASE 1266 drivers/gpu/drm/i915/i915_reg.h #define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
VLV_DISPLAY_BASE 2608 drivers/gpu/drm/i915/i915_reg.h #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
VLV_DISPLAY_BASE 2711 drivers/gpu/drm/i915/i915_reg.h #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
VLV_DISPLAY_BASE 2712 drivers/gpu/drm/i915/i915_reg.h #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
VLV_DISPLAY_BASE 2718 drivers/gpu/drm/i915/i915_reg.h #define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
VLV_DISPLAY_BASE 2721 drivers/gpu/drm/i915/i915_reg.h #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
VLV_DISPLAY_BASE 2722 drivers/gpu/drm/i915/i915_reg.h #define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
VLV_DISPLAY_BASE 2723 drivers/gpu/drm/i915/i915_reg.h #define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
VLV_DISPLAY_BASE 2724 drivers/gpu/drm/i915/i915_reg.h #define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
VLV_DISPLAY_BASE 2725 drivers/gpu/drm/i915/i915_reg.h #define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
VLV_DISPLAY_BASE 2726 drivers/gpu/drm/i915/i915_reg.h #define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
VLV_DISPLAY_BASE 2727 drivers/gpu/drm/i915/i915_reg.h #define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
VLV_DISPLAY_BASE 2904 drivers/gpu/drm/i915/i915_reg.h #define CHV_FUSE_GT			_MMIO(VLV_DISPLAY_BASE + 0x2168)
VLV_DISPLAY_BASE 3042 drivers/gpu/drm/i915/i915_reg.h #define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
VLV_DISPLAY_BASE 3046 drivers/gpu/drm/i915/i915_reg.h #define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
VLV_DISPLAY_BASE 3049 drivers/gpu/drm/i915/i915_reg.h #define _VLV_AUD_PORT_EN_B_DBG		(VLV_DISPLAY_BASE + 0x62F20)
VLV_DISPLAY_BASE 3050 drivers/gpu/drm/i915/i915_reg.h #define _VLV_AUD_PORT_EN_C_DBG		(VLV_DISPLAY_BASE + 0x62F30)
VLV_DISPLAY_BASE 3051 drivers/gpu/drm/i915/i915_reg.h #define _VLV_AUD_PORT_EN_D_DBG		(VLV_DISPLAY_BASE + 0x62F34)
VLV_DISPLAY_BASE 3297 drivers/gpu/drm/i915/i915_reg.h #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
VLV_DISPLAY_BASE 3299 drivers/gpu/drm/i915/i915_reg.h #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
VLV_DISPLAY_BASE 3310 drivers/gpu/drm/i915/i915_reg.h #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
VLV_DISPLAY_BASE 3395 drivers/gpu/drm/i915/i915_reg.h #define RAWCLK_FREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6024)
VLV_DISPLAY_BASE 3542 drivers/gpu/drm/i915/i915_reg.h #define FW_BLC_SELF_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6500)
VLV_DISPLAY_BASE 3545 drivers/gpu/drm/i915/i915_reg.h #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
VLV_DISPLAY_BASE 3547 drivers/gpu/drm/i915/i915_reg.h #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
VLV_DISPLAY_BASE 3552 drivers/gpu/drm/i915/i915_reg.h #define GCI_CONTROL		_MMIO(VLV_DISPLAY_BASE + 0x650C)
VLV_DISPLAY_BASE 3559 drivers/gpu/drm/i915/i915_reg.h #define GMBUSFREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6510)
VLV_DISPLAY_BASE 4343 drivers/gpu/drm/i915/i915_reg.h #define VLV_ADPA		_MMIO(VLV_DISPLAY_BASE + 0x61100)
VLV_DISPLAY_BASE 4492 drivers/gpu/drm/i915/i915_reg.h #define VLV_HDMIB	_MMIO(VLV_DISPLAY_BASE + 0x61140)
VLV_DISPLAY_BASE 4493 drivers/gpu/drm/i915/i915_reg.h #define VLV_HDMIC	_MMIO(VLV_DISPLAY_BASE + 0x61160)
VLV_DISPLAY_BASE 4494 drivers/gpu/drm/i915/i915_reg.h #define CHV_HDMID	_MMIO(VLV_DISPLAY_BASE + 0x6116C)
VLV_DISPLAY_BASE 4701 drivers/gpu/drm/i915/i915_reg.h #define VLV_PPS_BASE			(VLV_DISPLAY_BASE + PPS_BASE)
VLV_DISPLAY_BASE 5403 drivers/gpu/drm/i915/i915_reg.h #define VLV_DP_B		_MMIO(VLV_DISPLAY_BASE + 0x64100)
VLV_DISPLAY_BASE 5404 drivers/gpu/drm/i915/i915_reg.h #define VLV_DP_C		_MMIO(VLV_DISPLAY_BASE + 0x64200)
VLV_DISPLAY_BASE 5405 drivers/gpu/drm/i915/i915_reg.h #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
VLV_DISPLAY_BASE 5778 drivers/gpu/drm/i915/i915_reg.h #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
VLV_DISPLAY_BASE 5799 drivers/gpu/drm/i915/i915_reg.h #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
VLV_DISPLAY_BASE 5844 drivers/gpu/drm/i915/i915_reg.h #define DSPARB2				_MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
VLV_DISPLAY_BASE 5857 drivers/gpu/drm/i915/i915_reg.h #define DSPARB3				_MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
VLV_DISPLAY_BASE 5902 drivers/gpu/drm/i915/i915_reg.h #define DSPFW4		_MMIO(VLV_DISPLAY_BASE + 0x70070)
VLV_DISPLAY_BASE 5909 drivers/gpu/drm/i915/i915_reg.h #define DSPFW5		_MMIO(VLV_DISPLAY_BASE + 0x70074)
VLV_DISPLAY_BASE 5918 drivers/gpu/drm/i915/i915_reg.h #define DSPFW6		_MMIO(VLV_DISPLAY_BASE + 0x70078)
VLV_DISPLAY_BASE 5921 drivers/gpu/drm/i915/i915_reg.h #define DSPFW7		_MMIO(VLV_DISPLAY_BASE + 0x7007c)
VLV_DISPLAY_BASE 5922 drivers/gpu/drm/i915/i915_reg.h #define DSPFW7_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
VLV_DISPLAY_BASE 5931 drivers/gpu/drm/i915/i915_reg.h #define DSPFW8_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b8)
VLV_DISPLAY_BASE 5940 drivers/gpu/drm/i915/i915_reg.h #define DSPFW9_CHV	_MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
VLV_DISPLAY_BASE 5951 drivers/gpu/drm/i915/i915_reg.h #define DSPHOWM		_MMIO(VLV_DISPLAY_BASE + 0x70064)
VLV_DISPLAY_BASE 5972 drivers/gpu/drm/i915/i915_reg.h #define DSPHOWM1	_MMIO(VLV_DISPLAY_BASE + 0x70068)
VLV_DISPLAY_BASE 5995 drivers/gpu/drm/i915/i915_reg.h #define VLV_DDL(pipe)			_MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
VLV_DISPLAY_BASE 6003 drivers/gpu/drm/i915/i915_reg.h #define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
VLV_DISPLAY_BASE 6007 drivers/gpu/drm/i915/i915_reg.h #define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)
VLV_DISPLAY_BASE 6504 drivers/gpu/drm/i915/i915_reg.h #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
VLV_DISPLAY_BASE 6527 drivers/gpu/drm/i915/i915_reg.h #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
VLV_DISPLAY_BASE 6528 drivers/gpu/drm/i915/i915_reg.h #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
VLV_DISPLAY_BASE 6529 drivers/gpu/drm/i915/i915_reg.h #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
VLV_DISPLAY_BASE 6530 drivers/gpu/drm/i915/i915_reg.h #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
VLV_DISPLAY_BASE 6531 drivers/gpu/drm/i915/i915_reg.h #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
VLV_DISPLAY_BASE 6532 drivers/gpu/drm/i915/i915_reg.h #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
VLV_DISPLAY_BASE 6533 drivers/gpu/drm/i915/i915_reg.h #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
VLV_DISPLAY_BASE 6534 drivers/gpu/drm/i915/i915_reg.h #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
VLV_DISPLAY_BASE 6535 drivers/gpu/drm/i915/i915_reg.h #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
VLV_DISPLAY_BASE 6536 drivers/gpu/drm/i915/i915_reg.h #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
VLV_DISPLAY_BASE 6538 drivers/gpu/drm/i915/i915_reg.h #define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
VLV_DISPLAY_BASE 6541 drivers/gpu/drm/i915/i915_reg.h #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
VLV_DISPLAY_BASE 6544 drivers/gpu/drm/i915/i915_reg.h #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
VLV_DISPLAY_BASE 6546 drivers/gpu/drm/i915/i915_reg.h #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
VLV_DISPLAY_BASE 6547 drivers/gpu/drm/i915/i915_reg.h #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
VLV_DISPLAY_BASE 6548 drivers/gpu/drm/i915/i915_reg.h #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
VLV_DISPLAY_BASE 6549 drivers/gpu/drm/i915/i915_reg.h #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
VLV_DISPLAY_BASE 6550 drivers/gpu/drm/i915/i915_reg.h #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
VLV_DISPLAY_BASE 6551 drivers/gpu/drm/i915/i915_reg.h #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
VLV_DISPLAY_BASE 6552 drivers/gpu/drm/i915/i915_reg.h #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
VLV_DISPLAY_BASE 6553 drivers/gpu/drm/i915/i915_reg.h #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
VLV_DISPLAY_BASE 6554 drivers/gpu/drm/i915/i915_reg.h #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
VLV_DISPLAY_BASE 6555 drivers/gpu/drm/i915/i915_reg.h #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
VLV_DISPLAY_BASE 6556 drivers/gpu/drm/i915/i915_reg.h #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
VLV_DISPLAY_BASE 6557 drivers/gpu/drm/i915/i915_reg.h #define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
VLV_DISPLAY_BASE 6558 drivers/gpu/drm/i915/i915_reg.h #define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
VLV_DISPLAY_BASE 6559 drivers/gpu/drm/i915/i915_reg.h #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722e0)
VLV_DISPLAY_BASE 6589 drivers/gpu/drm/i915/i915_reg.h 	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
VLV_DISPLAY_BASE 6936 drivers/gpu/drm/i915/i915_reg.h #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
VLV_DISPLAY_BASE 8175 drivers/gpu/drm/i915/i915_reg.h #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
VLV_DISPLAY_BASE 8176 drivers/gpu/drm/i915/i915_reg.h #define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
VLV_DISPLAY_BASE 8177 drivers/gpu/drm/i915/i915_reg.h #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
VLV_DISPLAY_BASE 8179 drivers/gpu/drm/i915/i915_reg.h #define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
VLV_DISPLAY_BASE 8180 drivers/gpu/drm/i915/i915_reg.h #define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
VLV_DISPLAY_BASE 8181 drivers/gpu/drm/i915/i915_reg.h #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
VLV_DISPLAY_BASE 8183 drivers/gpu/drm/i915/i915_reg.h #define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
VLV_DISPLAY_BASE 8184 drivers/gpu/drm/i915/i915_reg.h #define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
VLV_DISPLAY_BASE 8185 drivers/gpu/drm/i915/i915_reg.h #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
VLV_DISPLAY_BASE 8759 drivers/gpu/drm/i915/i915_reg.h #define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
VLV_DISPLAY_BASE 9025 drivers/gpu/drm/i915/i915_reg.h #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
VLV_DISPLAY_BASE 9026 drivers/gpu/drm/i915/i915_reg.h #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
VLV_DISPLAY_BASE 9028 drivers/gpu/drm/i915/i915_reg.h #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
VLV_DISPLAY_BASE 9029 drivers/gpu/drm/i915/i915_reg.h #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
VLV_DISPLAY_BASE 9031 drivers/gpu/drm/i915/i915_reg.h #define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
VLV_DISPLAY_BASE 9045 drivers/gpu/drm/i915/i915_reg.h #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
VLV_DISPLAY_BASE 9046 drivers/gpu/drm/i915/i915_reg.h #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
VLV_DISPLAY_BASE 10288 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
VLV_DISPLAY_BASE 10289 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
VLV_DISPLAY_BASE 10290 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_A_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x67908)
VLV_DISPLAY_BASE 10291 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
VLV_DISPLAY_BASE 10292 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
VLV_DISPLAY_BASE 10293 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
VLV_DISPLAY_BASE 10294 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
VLV_DISPLAY_BASE 10295 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
VLV_DISPLAY_BASE 10300 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
VLV_DISPLAY_BASE 10301 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
VLV_DISPLAY_BASE 10302 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_B_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x69908)
VLV_DISPLAY_BASE 10303 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_B_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6990C)
VLV_DISPLAY_BASE 10304 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_B_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x69910)
VLV_DISPLAY_BASE 10305 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_B_DEGAMMA	(VLV_DISPLAY_BASE + 0x68000)
VLV_DISPLAY_BASE 10306 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_B_GAMMA	(VLV_DISPLAY_BASE + 0x69000)
VLV_DISPLAY_BASE 10307 drivers/gpu/drm/i915/i915_reg.h #define _CGM_PIPE_B_MODE	(VLV_DISPLAY_BASE + 0x69A00)
VLV_DISPLAY_BASE 10473 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
VLV_DISPLAY_BASE 10474 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
VLV_DISPLAY_BASE 10569 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
VLV_DISPLAY_BASE 10570 drivers/gpu/drm/i915/i915_reg.h #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
VLV_DISPLAY_BASE 10576 drivers/gpu/drm/i915/i915_reg.h #define _MIPIA_AUTOPWG			(VLV_DISPLAY_BASE + 0x611a0)