VLINE_ACK        3205 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
VLINE_ACK        3331 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
VLINE_ACK        2951 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 			WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
VLINE_ACK        7338 drivers/gpu/drm/radeon/cik.c 		WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
VLINE_ACK        7342 drivers/gpu/drm/radeon/cik.c 		WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
VLINE_ACK        7354 drivers/gpu/drm/radeon/cik.c 			WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
VLINE_ACK        7358 drivers/gpu/drm/radeon/cik.c 			WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
VLINE_ACK        7371 drivers/gpu/drm/radeon/cik.c 			WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
VLINE_ACK        7375 drivers/gpu/drm/radeon/cik.c 			WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
VLINE_ACK        4640 drivers/gpu/drm/radeon/evergreen.c 				       VLINE_ACK);
VLINE_ACK        6174 drivers/gpu/drm/radeon/si.c 				       VLINE_ACK);