VEBOX_RING_BASE   128 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			{ .gen = 7, .base = VEBOX_RING_BASE }
VEBOX_RING_BASE  1839 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
VEBOX_RING_BASE   128 drivers/gpu/drm/i915/gvt/mmio_context.c 	{VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
VEBOX_RING_BASE  2419 drivers/gpu/drm/i915/i915_reg.h #define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
VEBOX_RING_BASE  2420 drivers/gpu/drm/i915/i915_reg.h #define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
VEBOX_RING_BASE  2421 drivers/gpu/drm/i915/i915_reg.h #define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
VEBOX_RING_BASE   919 drivers/gpu/drm/i915/intel_uncore.c 	RING_TAIL(VEBOX_RING_BASE),	/* 0x1a000 (base) */