VCS0             2111 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 			 GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0));
VCS0             2136 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	[I915_EXEC_BSD]		= VCS0,
VCS0               87 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	[VCS0] = {
VCS0              158 drivers/gpu/drm/i915/gt/intel_engine_user.c 		[VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
VCS0             3067 drivers/gpu/drm/i915/gt/intel_lrc.c 			[VCS0]  = GEN8_VCS0_IRQ_SHIFT,
VCS0              331 drivers/gpu/drm/i915/gt/intel_mocs.c 	case VCS0:
VCS0              289 drivers/gpu/drm/i915/gt/intel_reset.c 		[VCS0]  = GEN6_GRDOM_MEDIA,
VCS0              412 drivers/gpu/drm/i915/gt/intel_reset.c 		[VCS0]  = GEN11_GRDOM_MEDIA,
VCS0              555 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		case VCS0:
VCS0              411 drivers/gpu/drm/i915/gvt/cmd_parser.c #define R_VCS1  BIT(VCS0)
VCS0              591 drivers/gpu/drm/i915/gvt/cmd_parser.c 	[VCS0] = {
VCS0             1091 drivers/gpu/drm/i915/gvt/cmd_parser.c 	[VCS0] = {
VCS0               52 drivers/gpu/drm/i915/gvt/execlist.c 	[VCS0]  = VCS_AS_CONTEXT_SWITCH,
VCS0              330 drivers/gpu/drm/i915/gvt/handlers.c 			engine_mask |= BIT(VCS0);
VCS0             1759 drivers/gpu/drm/i915/gvt/handlers.c 		id = VCS0;
VCS0              153 drivers/gpu/drm/i915/gvt/mmio_context.c 	[VCS0]  = 0xc900,
VCS0              340 drivers/gpu/drm/i915/gvt/mmio_context.c 	[VCS0]  = 0x4264,
VCS0              400 drivers/gpu/drm/i915/gvt/mmio_context.c 		[VCS0]  = 0xc900,
VCS0             2076 drivers/gpu/drm/i915/i915_drv.h 	ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
VCS0             1121 drivers/gpu/drm/i915/i915_gpu_error.c 			case VCS0:
VCS0             4294 drivers/gpu/drm/i915/i915_irq.c 			intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
VCS0              324 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0),
VCS0              334 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0),
VCS0              342 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0), \
VCS0              369 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
VCS0              417 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
VCS0              483 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
VCS0              493 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
VCS0              557 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
VCS0              566 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
VCS0              616 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
VCS0              633 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
VCS0              690 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
VCS0              711 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
VCS0              760 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
VCS0              767 drivers/gpu/drm/i915/i915_pci.c 	.engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
VCS0              799 drivers/gpu/drm/i915/i915_pci.c 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),