VCE_UENC_REG_CLOCK_GATING  116 drivers/gpu/drm/radeon/vce_v1_0.c 		tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
VCE_UENC_REG_CLOCK_GATING  118 drivers/gpu/drm/radeon/vce_v1_0.c 		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
VCE_UENC_REG_CLOCK_GATING  129 drivers/gpu/drm/radeon/vce_v1_0.c 		tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
VCE_UENC_REG_CLOCK_GATING  131 drivers/gpu/drm/radeon/vce_v1_0.c 		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
VCE_UENC_REG_CLOCK_GATING  152 drivers/gpu/drm/radeon/vce_v1_0.c 	tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
VCE_UENC_REG_CLOCK_GATING  154 drivers/gpu/drm/radeon/vce_v1_0.c 	WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
VCE_UENC_REG_CLOCK_GATING  224 drivers/gpu/drm/radeon/vce_v1_0.c 	WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
VCE_UENC_REG_CLOCK_GATING   51 drivers/gpu/drm/radeon/vce_v2_0.c 		tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
VCE_UENC_REG_CLOCK_GATING   53 drivers/gpu/drm/radeon/vce_v2_0.c 		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
VCE_UENC_REG_CLOCK_GATING   67 drivers/gpu/drm/radeon/vce_v2_0.c 		tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
VCE_UENC_REG_CLOCK_GATING   69 drivers/gpu/drm/radeon/vce_v2_0.c 		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
VCE_UENC_REG_CLOCK_GATING   93 drivers/gpu/drm/radeon/vce_v2_0.c 	orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
VCE_UENC_REG_CLOCK_GATING   96 drivers/gpu/drm/radeon/vce_v2_0.c 		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
VCE_UENC_REG_CLOCK_GATING  164 drivers/gpu/drm/radeon/vce_v2_0.c 	WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);