VCE_UENC_CLOCK_GATING  111 drivers/gpu/drm/radeon/vce_v1_0.c 		tmp = RREG32(VCE_UENC_CLOCK_GATING);
VCE_UENC_CLOCK_GATING  114 drivers/gpu/drm/radeon/vce_v1_0.c 		WREG32(VCE_UENC_CLOCK_GATING, tmp);
VCE_UENC_CLOCK_GATING  124 drivers/gpu/drm/radeon/vce_v1_0.c 		tmp = RREG32(VCE_UENC_CLOCK_GATING);
VCE_UENC_CLOCK_GATING  127 drivers/gpu/drm/radeon/vce_v1_0.c 		WREG32(VCE_UENC_CLOCK_GATING, tmp);
VCE_UENC_CLOCK_GATING  148 drivers/gpu/drm/radeon/vce_v1_0.c 	tmp = RREG32(VCE_UENC_CLOCK_GATING);
VCE_UENC_CLOCK_GATING  150 drivers/gpu/drm/radeon/vce_v1_0.c 	WREG32(VCE_UENC_CLOCK_GATING, tmp);
VCE_UENC_CLOCK_GATING  223 drivers/gpu/drm/radeon/vce_v1_0.c 	WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
VCE_UENC_CLOCK_GATING   47 drivers/gpu/drm/radeon/vce_v2_0.c 		tmp = RREG32(VCE_UENC_CLOCK_GATING);
VCE_UENC_CLOCK_GATING   49 drivers/gpu/drm/radeon/vce_v2_0.c 		WREG32(VCE_UENC_CLOCK_GATING, tmp);
VCE_UENC_CLOCK_GATING   62 drivers/gpu/drm/radeon/vce_v2_0.c 		tmp = RREG32(VCE_UENC_CLOCK_GATING);
VCE_UENC_CLOCK_GATING   65 drivers/gpu/drm/radeon/vce_v2_0.c 		WREG32(VCE_UENC_CLOCK_GATING, tmp);
VCE_UENC_CLOCK_GATING   87 drivers/gpu/drm/radeon/vce_v2_0.c 	orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
VCE_UENC_CLOCK_GATING   91 drivers/gpu/drm/radeon/vce_v2_0.c 		WREG32(VCE_UENC_CLOCK_GATING, tmp);
VCE_UENC_CLOCK_GATING  140 drivers/gpu/drm/radeon/vce_v2_0.c 	tmp = RREG32(VCE_UENC_CLOCK_GATING);
VCE_UENC_CLOCK_GATING  143 drivers/gpu/drm/radeon/vce_v2_0.c 	WREG32(VCE_UENC_CLOCK_GATING, tmp);
VCE_UENC_CLOCK_GATING  163 drivers/gpu/drm/radeon/vce_v2_0.c 	WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);