VC4_SET_FIELD 312 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD((mode->htotal - VC4_SET_FIELD 315 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD((mode->hsync_end - VC4_SET_FIELD 319 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD((mode->hsync_start - VC4_SET_FIELD 322 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE)); VC4_SET_FIELD 325 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, VC4_SET_FIELD 327 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, VC4_SET_FIELD 330 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, VC4_SET_FIELD 332 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); VC4_SET_FIELD 336 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->crtc_vtotal - VC4_SET_FIELD 339 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->crtc_vsync_end - VC4_SET_FIELD 343 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->crtc_vsync_start - VC4_SET_FIELD 346 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); VC4_SET_FIELD 357 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->htotal * pixel_rep / 2, VC4_SET_FIELD 369 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | VC4_SET_FIELD 370 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(vc4_get_fifo_full_level(format), VC4_SET_FIELD 372 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | VC4_SET_FIELD 376 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(vc4_encoder->clock_select, VC4_SET_FIELD 414 drivers/gpu/drm/vc4/vc4_crtc.c dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX); VC4_SET_FIELD 416 drivers/gpu/drm/vc4/vc4_crtc.c dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); VC4_SET_FIELD 568 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) | VC4_SET_FIELD 569 drivers/gpu/drm/vc4/vc4_crtc.c VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) | VC4_SET_FIELD 159 drivers/gpu/drm/vc4/vc4_dpi.c dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, VC4_SET_FIELD 163 drivers/gpu/drm/vc4/vc4_dpi.c dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, VC4_SET_FIELD 165 drivers/gpu/drm/vc4/vc4_dpi.c dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); VC4_SET_FIELD 168 drivers/gpu/drm/vc4/vc4_dpi.c dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, VC4_SET_FIELD 172 drivers/gpu/drm/vc4/vc4_dpi.c dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, VC4_SET_FIELD 176 drivers/gpu/drm/vc4/vc4_dpi.c dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3, VC4_SET_FIELD 185 drivers/gpu/drm/vc4/vc4_dpi.c dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT); VC4_SET_FIELD 871 drivers/gpu/drm/vc4/vc4_dsi.c u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | VC4_SET_FIELD 872 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); VC4_SET_FIELD 883 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | VC4_SET_FIELD 884 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | VC4_SET_FIELD 885 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); VC4_SET_FIELD 887 drivers/gpu/drm/vc4/vc4_dsi.c u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | VC4_SET_FIELD 888 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | VC4_SET_FIELD 889 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | VC4_SET_FIELD 890 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | VC4_SET_FIELD 891 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) | VC4_SET_FIELD 892 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) | VC4_SET_FIELD 893 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3)); VC4_SET_FIELD 952 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0), VC4_SET_FIELD 954 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8), VC4_SET_FIELD 956 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0), VC4_SET_FIELD 960 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0), VC4_SET_FIELD 962 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52), VC4_SET_FIELD 966 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0), VC4_SET_FIELD 970 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0), VC4_SET_FIELD 972 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6), VC4_SET_FIELD 974 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4), VC4_SET_FIELD 978 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0), VC4_SET_FIELD 980 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8), VC4_SET_FIELD 983 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT)); VC4_SET_FIELD 994 drivers/gpu/drm/vc4/vc4_dsi.c DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, VC4_SET_FIELD 999 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) | VC4_SET_FIELD 1000 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) | VC4_SET_FIELD 1001 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) | VC4_SET_FIELD 1002 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX)); VC4_SET_FIELD 1005 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi_esc_timing(1000000), VC4_SET_FIELD 1017 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : VC4_SET_FIELD 1018 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT))); VC4_SET_FIELD 1037 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE, VC4_SET_FIELD 1061 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi->divider, VC4_SET_FIELD 1063 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | VC4_SET_FIELD 1064 drivers/gpu/drm/vc4/vc4_dsi.c VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME, VC4_SET_FIELD 1095 drivers/gpu/drm/vc4/vc4_dsi.c pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT); VC4_SET_FIELD 1096 drivers/gpu/drm/vc4/vc4_dsi.c pkth |= VC4_SET_FIELD(packet.header[1] | VC4_SET_FIELD 1121 drivers/gpu/drm/vc4/vc4_dsi.c pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO); VC4_SET_FIELD 1125 drivers/gpu/drm/vc4/vc4_dsi.c pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX, VC4_SET_FIELD 1128 drivers/gpu/drm/vc4/vc4_dsi.c pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX, VC4_SET_FIELD 1152 drivers/gpu/drm/vc4/vc4_dsi.c pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT); VC4_SET_FIELD 1156 drivers/gpu/drm/vc4/vc4_dsi.c pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY, VC4_SET_FIELD 1159 drivers/gpu/drm/vc4/vc4_dsi.c pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT, VC4_SET_FIELD 441 drivers/gpu/drm/vc4/vc4_gem.c VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | VC4_SET_FIELD 442 drivers/gpu/drm/vc4/vc4_gem.c VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | VC4_SET_FIELD 443 drivers/gpu/drm/vc4/vc4_gem.c VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | VC4_SET_FIELD 444 drivers/gpu/drm/vc4/vc4_gem.c VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); VC4_SET_FIELD 456 drivers/gpu/drm/vc4/vc4_gem.c VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | VC4_SET_FIELD 457 drivers/gpu/drm/vc4/vc4_gem.c VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC)); VC4_SET_FIELD 481 drivers/gpu/drm/vc4/vc4_hdmi.c u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, VC4_SET_FIELD 483 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, VC4_SET_FIELD 485 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); VC4_SET_FIELD 486 drivers/gpu/drm/vc4/vc4_hdmi.c u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | VC4_SET_FIELD 487 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, VC4_SET_FIELD 489 drivers/gpu/drm/vc4/vc4_hdmi.c u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | VC4_SET_FIELD 490 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(mode->crtc_vtotal - VC4_SET_FIELD 548 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(mode->hdisplay * pixel_rep, VC4_SET_FIELD 552 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD((mode->htotal - VC4_SET_FIELD 555 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD((mode->hsync_end - VC4_SET_FIELD 558 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD((mode->hsync_start - VC4_SET_FIELD 572 drivers/gpu/drm/vc4/vc4_hdmi.c csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, VC4_SET_FIELD 590 drivers/gpu/drm/vc4/vc4_hdmi.c csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, VC4_SET_FIELD 728 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | VC4_SET_FIELD 729 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); VC4_SET_FIELD 750 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); VC4_SET_FIELD 867 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); VC4_SET_FIELD 870 drivers/gpu/drm/vc4/vc4_hdmi.c audio_packet_config |= VC4_SET_FIELD(channel_mask, VC4_SET_FIELD 876 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | VC4_SET_FIELD 877 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); VC4_SET_FIELD 880 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | VC4_SET_FIELD 881 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); VC4_SET_FIELD 884 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | VC4_SET_FIELD 885 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | VC4_SET_FIELD 886 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | VC4_SET_FIELD 887 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); VC4_SET_FIELD 892 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); VC4_SET_FIELD 922 drivers/gpu/drm/vc4/vc4_hdmi.c VC4_SET_FIELD(hdmi->audio.channels, VC4_SET_FIELD 296 drivers/gpu/drm/vc4/vc4_hvs.c dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); VC4_SET_FIELD 121 drivers/gpu/drm/vc4/vc4_kms.c VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), VC4_SET_FIELD 123 drivers/gpu/drm/vc4/vc4_kms.c VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), VC4_SET_FIELD 125 drivers/gpu/drm/vc4/vc4_kms.c VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), VC4_SET_FIELD 128 drivers/gpu/drm/vc4/vc4_kms.c VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), VC4_SET_FIELD 130 drivers/gpu/drm/vc4/vc4_kms.c VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), VC4_SET_FIELD 132 drivers/gpu/drm/vc4/vc4_kms.c VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), VC4_SET_FIELD 135 drivers/gpu/drm/vc4/vc4_kms.c VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), VC4_SET_FIELD 137 drivers/gpu/drm/vc4/vc4_kms.c VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), VC4_SET_FIELD 139 drivers/gpu/drm/vc4/vc4_kms.c VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), VC4_SET_FIELD 144 drivers/gpu/drm/vc4/vc4_kms.c VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); VC4_SET_FIELD 406 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | VC4_SET_FIELD 407 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); VC4_SET_FIELD 409 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); VC4_SET_FIELD 418 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | VC4_SET_FIELD 419 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); VC4_SET_FIELD 637 drivers/gpu/drm/vc4/vc4_plane.c pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH); VC4_SET_FIELD 700 drivers/gpu/drm/vc4/vc4_plane.c pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) | VC4_SET_FIELD 701 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) | VC4_SET_FIELD 702 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) | VC4_SET_FIELD 703 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R)); VC4_SET_FIELD 769 drivers/gpu/drm/vc4/vc4_plane.c pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT); VC4_SET_FIELD 784 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) | VC4_SET_FIELD 787 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | VC4_SET_FIELD 789 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) | VC4_SET_FIELD 790 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1)); VC4_SET_FIELD 795 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) | VC4_SET_FIELD 796 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) | VC4_SET_FIELD 797 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y)); VC4_SET_FIELD 802 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(vc4_state->crtc_w, VC4_SET_FIELD 804 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(vc4_state->crtc_h, VC4_SET_FIELD 818 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(fb->format->has_alpha ? VC4_SET_FIELD 824 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) | VC4_SET_FIELD 825 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT)); VC4_SET_FIELD 850 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(fb->pitches[i], VC4_SET_FIELD 893 drivers/gpu/drm/vc4/vc4_plane.c u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start, VC4_SET_FIELD 908 drivers/gpu/drm/vc4/vc4_plane.c VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE); VC4_SET_FIELD 84 drivers/gpu/drm/vc4/vc4_render_cl.c VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, VC4_SET_FIELD 289 drivers/gpu/drm/vc4/vc4_txp.c VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | VC4_SET_FIELD 290 drivers/gpu/drm/vc4/vc4_txp.c VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); VC4_SET_FIELD 299 drivers/gpu/drm/vc4/vc4_txp.c VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | VC4_SET_FIELD 300 drivers/gpu/drm/vc4/vc4_txp.c VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); VC4_SET_FIELD 409 drivers/gpu/drm/vc4/vc4_validate.c VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, VC4_SET_FIELD 411 drivers/gpu/drm/vc4/vc4_validate.c VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128,