VAL 106 arch/arm/include/asm/hw_breakpoint.h #define ARM_DBG_READ(N, M, OP2, VAL) do {\ VAL 107 arch/arm/include/asm/hw_breakpoint.h asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\ VAL 110 arch/arm/include/asm/hw_breakpoint.h #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ VAL 111 arch/arm/include/asm/hw_breakpoint.h asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\ VAL 48 arch/arm/kernel/hw_breakpoint.c #define READ_WB_REG_CASE(OP2, M, VAL) \ VAL 50 arch/arm/kernel/hw_breakpoint.c ARM_DBG_READ(c0, c ## M, OP2, VAL); \ VAL 53 arch/arm/kernel/hw_breakpoint.c #define WRITE_WB_REG_CASE(OP2, M, VAL) \ VAL 55 arch/arm/kernel/hw_breakpoint.c ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \ VAL 58 arch/arm/kernel/hw_breakpoint.c #define GEN_READ_WB_REG_CASES(OP2, VAL) \ VAL 59 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 0, VAL); \ VAL 60 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 1, VAL); \ VAL 61 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 2, VAL); \ VAL 62 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 3, VAL); \ VAL 63 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 4, VAL); \ VAL 64 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 5, VAL); \ VAL 65 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 6, VAL); \ VAL 66 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 7, VAL); \ VAL 67 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 8, VAL); \ VAL 68 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 9, VAL); \ VAL 69 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 10, VAL); \ VAL 70 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 11, VAL); \ VAL 71 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 12, VAL); \ VAL 72 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 13, VAL); \ VAL 73 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 14, VAL); \ VAL 74 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 15, VAL) VAL 76 arch/arm/kernel/hw_breakpoint.c #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ VAL 77 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 0, VAL); \ VAL 78 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 1, VAL); \ VAL 79 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 2, VAL); \ VAL 80 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 3, VAL); \ VAL 81 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 4, VAL); \ VAL 82 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 5, VAL); \ VAL 83 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 6, VAL); \ VAL 84 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 7, VAL); \ VAL 85 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 8, VAL); \ VAL 86 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 9, VAL); \ VAL 87 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 10, VAL); \ VAL 88 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 11, VAL); \ VAL 89 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 12, VAL); \ VAL 90 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 13, VAL); \ VAL 91 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 14, VAL); \ VAL 92 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 15, VAL) VAL 133 arch/arm64/include/asm/barrier.h typeof(*ptr) VAL; \ VAL 135 arch/arm64/include/asm/barrier.h VAL = READ_ONCE(*__PTR); \ VAL 138 arch/arm64/include/asm/barrier.h __cmpwait_relaxed(__PTR, VAL); \ VAL 140 arch/arm64/include/asm/barrier.h VAL; \ VAL 146 arch/arm64/include/asm/barrier.h typeof(*ptr) VAL; \ VAL 148 arch/arm64/include/asm/barrier.h VAL = smp_load_acquire(__PTR); \ VAL 151 arch/arm64/include/asm/barrier.h __cmpwait_relaxed(__PTR, VAL); \ VAL 153 arch/arm64/include/asm/barrier.h VAL; \ VAL 99 arch/arm64/include/asm/hw_breakpoint.h #define AARCH64_DBG_READ(N, REG, VAL) do {\ VAL 100 arch/arm64/include/asm/hw_breakpoint.h VAL = read_sysreg(dbg##REG##N##_el1);\ VAL 103 arch/arm64/include/asm/hw_breakpoint.h #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ VAL 104 arch/arm64/include/asm/hw_breakpoint.h write_sysreg(VAL, dbg##REG##N##_el1);\ VAL 59 arch/arm64/kernel/hw_breakpoint.c #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ VAL 61 arch/arm64/kernel/hw_breakpoint.c AARCH64_DBG_READ(N, REG, VAL); \ VAL 64 arch/arm64/kernel/hw_breakpoint.c #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ VAL 66 arch/arm64/kernel/hw_breakpoint.c AARCH64_DBG_WRITE(N, REG, VAL); \ VAL 69 arch/arm64/kernel/hw_breakpoint.c #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ VAL 70 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 0, REG, VAL); \ VAL 71 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 1, REG, VAL); \ VAL 72 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 2, REG, VAL); \ VAL 73 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 3, REG, VAL); \ VAL 74 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 4, REG, VAL); \ VAL 75 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 5, REG, VAL); \ VAL 76 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 6, REG, VAL); \ VAL 77 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 7, REG, VAL); \ VAL 78 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 8, REG, VAL); \ VAL 79 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 9, REG, VAL); \ VAL 80 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 10, REG, VAL); \ VAL 81 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 11, REG, VAL); \ VAL 82 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 12, REG, VAL); \ VAL 83 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 13, REG, VAL); \ VAL 84 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 14, REG, VAL); \ VAL 85 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 15, REG, VAL) VAL 87 arch/arm64/kernel/hw_breakpoint.c #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \ VAL 88 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \ VAL 89 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \ VAL 90 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \ VAL 91 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \ VAL 92 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \ VAL 93 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \ VAL 94 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \ VAL 95 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \ VAL 96 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \ VAL 97 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \ VAL 98 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \ VAL 99 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \ VAL 100 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \ VAL 101 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \ VAL 102 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \ VAL 103 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 15, REG, VAL) VAL 113 arch/sparc/include/asm/tsb.h #define TSB_STORE(ADDR, VAL) \ VAL 114 arch/sparc/include/asm/tsb.h 661: stxa VAL, [ADDR] ASI_N; \ VAL 117 arch/sparc/include/asm/tsb.h stxa VAL, [ADDR] ASI_PHYS_USE_EC; \ VAL 279 drivers/block/skd_main.c #define SKD_WRITEL(DEV, VAL, OFF) skd_reg_write32(DEV, VAL, OFF) VAL 281 drivers/block/skd_main.c #define SKD_WRITEQ(DEV, VAL, OFF) skd_reg_write64(DEV, VAL, OFF) VAL 95 drivers/gpio/gpio-it87.c outb(0x02, VAL); VAL 102 drivers/gpio/gpio-it87.c outb(ldn, VAL); VAL 108 drivers/gpio/gpio-it87.c return inb(VAL); VAL 114 drivers/gpio/gpio-it87.c outb(val, VAL); VAL 122 drivers/gpio/gpio-it87.c val = inb(VAL) << 8; VAL 124 drivers/gpio/gpio-it87.c val |= inb(VAL); VAL 131 drivers/gpio/gpio-it87.c outb(val >> 8, VAL); VAL 133 drivers/gpio/gpio-it87.c outb(val, VAL); VAL 74 drivers/gpu/drm/panel/panel-novatek-nt39016.c #define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 } VAL 47 drivers/hwmon/smsc47b397.c outb(val, VAL); VAL 53 drivers/hwmon/smsc47b397.c return inb(VAL); VAL 50 drivers/hwmon/smsc47m1.c outb(val, VAL); VAL 57 drivers/hwmon/smsc47m1.c return inb(VAL); VAL 1020 drivers/iommu/arm-smmu-v3.c val = atomic_cond_read_relaxed(&cmdq->lock, VAL >= 0); VAL 1133 drivers/iommu/arm-smmu-v3.c atomic_long_cond_read_relaxed(ptr, (VAL & mask) == valid); VAL 1205 drivers/iommu/arm-smmu-v3.c smp_cond_load_relaxed(cmd, !VAL || (ret = queue_poll(&qp))); VAL 1373 drivers/iommu/arm-smmu-v3.c atomic_cond_read_relaxed(&cmdq->owner_prod, VAL == llq.prod); VAL 74 drivers/net/ethernet/freescale/fs_enet/mac-fcc.c #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) VAL 47 drivers/net/ethernet/freescale/fs_enet/mii-fec.c #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) VAL 629 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c errcode = CMDQ_WQE_ERRCODE_GET(be32_to_cpu(status->status_info), VAL); VAL 950 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_DIMM_MEMTYPE(VAL) ((VAL >> 3) & 0xf) VAL 951 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_DIMM_NUMROWS(VAL) ((VAL >> 7) & 0xf) VAL 952 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_DIMM_NUMCOLS(VAL) ((VAL >> 11) & 0xf) VAL 953 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_DIMM_NUMRANKS(VAL) ((VAL >> 15) & 0x3) VAL 954 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_DIMM_DATAWIDTH(VAL) ((VAL >> 18) & 0x3) VAL 955 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_DIMM_NUMBANKS(VAL) ((VAL >> 21) & 0xf) VAL 956 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_DIMM_TYPE(VAL) ((VAL >> 25) & 0x3f) VAL 991 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) VAL 883 drivers/net/ethernet/qlogic/qlcnic/qlcnic.h #define QLCNIC_IS_LB_CONFIGURED(VAL) \ VAL 884 drivers/net/ethernet/qlogic/qlcnic/qlcnic.h (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) VAL 406 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) VAL 407 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2)) VAL 642 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) VAL 643 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) VAL 644 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) VAL 645 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) VAL 646 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) VAL 648 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4))) VAL 649 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4)) VAL 679 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) VAL 289 drivers/scsi/aha152x.h #define SETPORT(PORT, VAL) outb( (VAL), (PORT) ) VAL 117 drivers/scsi/esp_scsi.c #define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG) VAL 50 drivers/scsi/mac_esp.c #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG) VAL 705 drivers/scsi/qla2xxx/qla_nx.h #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) VAL 706 drivers/scsi/qla2xxx/qla_nx.h #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) VAL 764 drivers/scsi/qla4xxx/ql4_nx.h #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) VAL 765 drivers/scsi/qla4xxx/ql4_nx.h #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) VAL 45 drivers/scsi/sun3x_esp.c #define dma_write32(VAL, REG) \ VAL 46 drivers/scsi/sun3x_esp.c writel((VAL), esp->dma_regs + (REG)) VAL 50 drivers/scsi/sun3x_esp.c #define dma_write32(VAL, REG) \ VAL 51 drivers/scsi/sun3x_esp.c do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0) VAL 33 drivers/scsi/sun_esp.c #define dma_write32(VAL, REG) \ VAL 34 drivers/scsi/sun_esp.c sbus_writel((VAL), esp->dma_regs + (REG)) VAL 447 drivers/staging/comedi/drivers/s626.h #define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) VAL 448 drivers/staging/comedi/drivers/s626.h #define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) VAL 449 drivers/staging/comedi/drivers/s626.h #define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) VAL 1123 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskDWord); VAL 1127 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord); VAL 1131 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord); VAL 1138 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); VAL 1141 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; VAL 1152 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); VAL 1157 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); VAL 1207 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); VAL 1211 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord); VAL 1215 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord); VAL 1222 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; VAL 1224 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); VAL 1234 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord); VAL 1239 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff); VAL 1254 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && VAL 1255 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) && VAL 1256 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && VAL 1257 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0) VAL 1261 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]); VAL 1262 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); VAL 1263 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]); VAL 1265 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]); VAL 1266 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]); VAL 1269 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]); VAL 1270 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); VAL 1271 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]); VAL 1273 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]); VAL 1274 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]); VAL 96 drivers/watchdog/it8712f_wdt.c return inb(VAL); VAL 102 drivers/watchdog/it8712f_wdt.c outb(val, VAL); VAL 109 drivers/watchdog/it8712f_wdt.c val = inb(VAL) << 8; VAL 111 drivers/watchdog/it8712f_wdt.c val |= inb(VAL); VAL 118 drivers/watchdog/it8712f_wdt.c outb(ldn, VAL); VAL 139 drivers/watchdog/it8712f_wdt.c outb(0x02, VAL); VAL 120 drivers/watchdog/it87_wdt.c outb(0x02, VAL); VAL 127 drivers/watchdog/it87_wdt.c outb(ldn, VAL); VAL 133 drivers/watchdog/it87_wdt.c return inb(VAL); VAL 139 drivers/watchdog/it87_wdt.c outb(val, VAL); VAL 146 drivers/watchdog/it87_wdt.c val = inb(VAL) << 8; VAL 148 drivers/watchdog/it87_wdt.c val |= inb(VAL); VAL 155 drivers/watchdog/it87_wdt.c outb(val >> 8, VAL); VAL 157 drivers/watchdog/it87_wdt.c outb(val, VAL); VAL 149 fs/erofs/internal.h VAL != EROFS_LOCKED_MAGIC); VAL 232 include/asm-generic/barrier.h typeof(*ptr) VAL; \ VAL 234 include/asm-generic/barrier.h VAL = READ_ONCE(*__PTR); \ VAL 239 include/asm-generic/barrier.h VAL; \ VAL 812 include/linux/dma-mapping.h #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) VAL 814 include/linux/dma-mapping.h #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) VAL 819 include/linux/dma-mapping.h #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) VAL 821 include/linux/dma-mapping.h #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) VAL 85 include/uapi/linux/btf.h #define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24) VAL 86 include/uapi/linux/btf.h #define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16) VAL 87 include/uapi/linux/btf.h #define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff) VAL 250 kernel/bpf/helpers.c atomic_cond_read_relaxed(l, !VAL); VAL 34 kernel/locking/mcs_spinlock.h smp_cond_load_acquire(l, VAL); \ VAL 33 kernel/locking/qrwlock.c atomic_cond_read_acquire(&lock->cnts, !(VAL & _QW_LOCKED)); VAL 49 kernel/locking/qrwlock.c atomic_cond_read_acquire(&lock->cnts, !(VAL & _QW_LOCKED)); VAL 77 kernel/locking/qrwlock.c atomic_cond_read_acquire(&lock->cnts, VAL == _QW_WAITING); VAL 337 kernel/locking/qspinlock.c (VAL != _Q_PENDING_VAL) || !cnt--); VAL 381 kernel/locking/qspinlock.c atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_MASK)); VAL 510 kernel/locking/qspinlock.c val = atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK)); VAL 550 kernel/locking/qspinlock.c next = smp_cond_load_relaxed(&node->next, (VAL)); VAL 2613 kernel/sched/core.c smp_cond_load_acquire(&p->on_cpu, !VAL); VAL 109 kernel/smp.c smp_cond_load_acquire(&csd->flags, !(VAL & CSD_FLAG_LOCK)); VAL 85 tools/include/uapi/linux/btf.h #define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24) VAL 86 tools/include/uapi/linux/btf.h #define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16) VAL 87 tools/include/uapi/linux/btf.h #define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff)