BLT_RING_BASE      84 drivers/gpu/drm/i915/gt/intel_engine_cs.c 			{ .gen = 6, .base = BLT_RING_BASE }
BLT_RING_BASE    1837 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
BLT_RING_BASE      68 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
BLT_RING_BASE      69 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
BLT_RING_BASE      70 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
BLT_RING_BASE      71 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
BLT_RING_BASE      72 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
BLT_RING_BASE     120 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
BLT_RING_BASE     121 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
BLT_RING_BASE     122 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
BLT_RING_BASE     123 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
BLT_RING_BASE     124 drivers/gpu/drm/i915/gvt/mmio_context.c 	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
BLT_RING_BASE     631 drivers/gpu/drm/i915/i915_cmd_parser.c 	REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
BLT_RING_BASE     664 drivers/gpu/drm/i915/i915_cmd_parser.c 	REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
BLT_RING_BASE     671 drivers/gpu/drm/i915/i915_cmd_parser.c 	REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
BLT_RING_BASE    2416 drivers/gpu/drm/i915/i915_reg.h #define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))
BLT_RING_BASE    2417 drivers/gpu/drm/i915/i915_reg.h #define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))
BLT_RING_BASE    2418 drivers/gpu/drm/i915/i915_reg.h #define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
BLT_RING_BASE     920 drivers/gpu/drm/i915/intel_uncore.c 	RING_TAIL(BLT_RING_BASE),	/* 0x22000 (base) */
BLT_RING_BASE     928 drivers/gpu/drm/i915/intel_uncore.c 	RING_TAIL(BLT_RING_BASE),		/* 0x22000 (base) */