V2 44 arch/powerpc/lib/xor_vmx.c #define XOR(V1, V2) \ V2 46 arch/powerpc/lib/xor_vmx.c V1##_0 = vec_xor(V1##_0, V2##_0); \ V2 47 arch/powerpc/lib/xor_vmx.c V1##_1 = vec_xor(V1##_1, V2##_1); \ V2 48 arch/powerpc/lib/xor_vmx.c V1##_2 = vec_xor(V1##_2, V2##_2); \ V2 49 arch/powerpc/lib/xor_vmx.c V1##_3 = vec_xor(V1##_3, V2##_3); \ V2 985 drivers/isdn/hardware/mISDN/avmfritz.c ASSIGN_FUNC(V2, ISAC, fc->isac); V2 759 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SIG_EXPR_LIST_ALIAS(V2, VPICLK, VPI); V2 760 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SIG_EXPR_LIST_DECL_SINGLE(V2, NRTS1, NRTS1, V2_DESC); V2 761 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c PIN_DECL_2(V2, GPIOL5, VPICLK, NRTS1); V2 762 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c FUNC_GROUP_DECL(NRTS1, V2); V2 1032 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, V2 1034 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, V2 1037 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1, V2 2101 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c ASPEED_PINCTRL_PIN(V2), V2 807 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c SIG_EXPR_LIST_DECL_SINGLE(V2, DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC); V2 808 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c SIG_EXPR_LIST_DECL_SINGLE(V2, PWM0, PWM0, V2_DESC, COND2); V2 809 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c PIN_DECL_2(V2, GPION0, DASHN0, PWM0); V2 810 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c FUNC_GROUP_DECL(PWM0, V2); V2 2107 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c ASPEED_PINCTRL_PIN(V2), V2 2537 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c { PIN_CONFIG_BIAS_PULL_DOWN, { V2, T4 }, SCU8C, 29 }, V2 2538 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c { PIN_CONFIG_BIAS_DISABLE, { V2, T4 }, SCU8C, 29 }, V2 114 drivers/regulator/pcap-regulator.c VREG_INFO(V2, PCAP_REG_VREG1, 5, 6, 19, 22), V2 230 drivers/regulator/pcap-regulator.c VREG(V1), VREG(V2), VREG(V3), VREG(V4), VREG(V5), VREG(V6), VREG(V7),