UvdBootLevel 1515 drivers/gpu/drm/amd/amdgpu/kv_dpm.c offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), UvdBootLevel 279 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint8_t UvdBootLevel; UvdBootLevel 263 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h uint8_t UvdBootLevel; UvdBootLevel 297 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint8_t UvdBootLevel; UvdBootLevel 303 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint8_t UvdBootLevel; UvdBootLevel 337 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h uint8_t UvdBootLevel; UvdBootLevel 240 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h uint8_t UvdBootLevel; UvdBootLevel 2010 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->UvdBootLevel = 0; UvdBootLevel 2869 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.UvdBootLevel = 0; UvdBootLevel 2871 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.UvdBootLevel = uvd_table->count - 1; UvdBootLevel 2874 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c UvdBootLevel, smu_data->smc_state_table.UvdBootLevel); UvdBootLevel 1570 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c table->UvdBootLevel = 0; UvdBootLevel 2329 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c case UvdBootLevel: UvdBootLevel 2330 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel); UvdBootLevel 2375 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.UvdBootLevel = 0; UvdBootLevel 2377 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c smu_data->smc_state_table.UvdBootLevel = UvdBootLevel 2380 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c UvdBootLevel); UvdBootLevel 2386 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; UvdBootLevel 2396 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); UvdBootLevel 1406 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->UvdBootLevel = 0; UvdBootLevel 2184 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.UvdBootLevel = 0; UvdBootLevel 2186 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->smc_state_table.UvdBootLevel = UvdBootLevel 2189 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c UvdBootLevel); UvdBootLevel 2195 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; UvdBootLevel 2205 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); UvdBootLevel 2344 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c case UvdBootLevel: UvdBootLevel 2345 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel); UvdBootLevel 1321 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->UvdBootLevel = 0; UvdBootLevel 2637 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c case UvdBootLevel: UvdBootLevel 2638 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); UvdBootLevel 2683 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.UvdBootLevel = 0; UvdBootLevel 2685 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.UvdBootLevel = UvdBootLevel 2688 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); UvdBootLevel 2694 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; UvdBootLevel 2705 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); UvdBootLevel 338 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.UvdBootLevel = 0; UvdBootLevel 340 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c smu_data->smc_state_table.UvdBootLevel = UvdBootLevel 343 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c UvdBootLevel); UvdBootLevel 349 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; UvdBootLevel 359 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); UvdBootLevel 1330 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->UvdBootLevel = 0; UvdBootLevel 2192 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c case UvdBootLevel: UvdBootLevel 2193 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel); UvdBootLevel 3622 drivers/gpu/drm/radeon/ci_dpm.c table->UvdBootLevel = 0; UvdBootLevel 4085 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.UvdBootLevel = 0; UvdBootLevel 4087 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.UvdBootLevel = UvdBootLevel 4092 drivers/gpu/drm/radeon/ci_dpm.c tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); UvdBootLevel 1447 drivers/gpu/drm/radeon/kv_dpm.c offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), UvdBootLevel 336 drivers/gpu/drm/radeon/smu7_discrete.h uint8_t UvdBootLevel; UvdBootLevel 240 drivers/gpu/drm/radeon/smu7_fusion.h uint8_t UvdBootLevel;