UVD_RBC_RB_CNTL   394 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
UVD_RBC_RB_CNTL   395 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
UVD_RBC_RB_CNTL   396 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
UVD_RBC_RB_CNTL   397 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
UVD_RBC_RB_CNTL   398 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
UVD_RBC_RB_CNTL   399 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
UVD_RBC_RB_CNTL   812 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
UVD_RBC_RB_CNTL   813 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
UVD_RBC_RB_CNTL   814 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
UVD_RBC_RB_CNTL   815 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
UVD_RBC_RB_CNTL   816 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
UVD_RBC_RB_CNTL   817 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
UVD_RBC_RB_CNTL   838 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 	WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
UVD_RBC_RB_CNTL   895 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
UVD_RBC_RB_CNTL   896 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
UVD_RBC_RB_CNTL  1062 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
UVD_RBC_RB_CNTL  1063 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
UVD_RBC_RB_CNTL  1064 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
UVD_RBC_RB_CNTL  1065 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
UVD_RBC_RB_CNTL  1066 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
UVD_RBC_RB_CNTL  1067 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
UVD_RBC_RB_CNTL   905 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
UVD_RBC_RB_CNTL   906 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
UVD_RBC_RB_CNTL   907 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
UVD_RBC_RB_CNTL   908 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
UVD_RBC_RB_CNTL   909 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
UVD_RBC_RB_CNTL  1078 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
UVD_RBC_RB_CNTL  1079 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
UVD_RBC_RB_CNTL  1080 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
UVD_RBC_RB_CNTL  1081 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
UVD_RBC_RB_CNTL  1082 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
UVD_RBC_RB_CNTL  1022 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
UVD_RBC_RB_CNTL  1023 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
UVD_RBC_RB_CNTL  1024 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
UVD_RBC_RB_CNTL  1025 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
UVD_RBC_RB_CNTL  1026 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
UVD_RBC_RB_CNTL  1187 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
UVD_RBC_RB_CNTL  1188 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
UVD_RBC_RB_CNTL  1189 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
UVD_RBC_RB_CNTL  1190 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
UVD_RBC_RB_CNTL  1191 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
UVD_RBC_RB_CNTL   848 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
UVD_RBC_RB_CNTL   849 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
UVD_RBC_RB_CNTL   850 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
UVD_RBC_RB_CNTL   851 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
UVD_RBC_RB_CNTL   852 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
UVD_RBC_RB_CNTL   358 drivers/gpu/drm/radeon/uvd_v1_0.c 	WREG32(UVD_RBC_RB_CNTL, 0x11010101);
UVD_RBC_RB_CNTL   379 drivers/gpu/drm/radeon/uvd_v1_0.c 	WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
UVD_RBC_RB_CNTL   394 drivers/gpu/drm/radeon/uvd_v1_0.c 	WREG32(UVD_RBC_RB_CNTL, 0x11010101);