UPLL_RESET_MASK  1226 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
UPLL_RESET_MASK  1235 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
UPLL_RESET_MASK  1260 drivers/gpu/drm/radeon/evergreen.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
UPLL_RESET_MASK   215 drivers/gpu/drm/radeon/r600.c 		 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
UPLL_RESET_MASK   248 drivers/gpu/drm/radeon/r600.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
UPLL_RESET_MASK   272 drivers/gpu/drm/radeon/r600.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
UPLL_RESET_MASK    85 drivers/gpu/drm/radeon/rv770.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
UPLL_RESET_MASK    96 drivers/gpu/drm/radeon/rv770.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
UPLL_RESET_MASK   114 drivers/gpu/drm/radeon/rv770.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
UPLL_RESET_MASK  7031 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
UPLL_RESET_MASK  7040 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
UPLL_RESET_MASK  7065 drivers/gpu/drm/radeon/si.c 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);