UPDATE_VAL 229 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0)); UPDATE_VAL 235 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1)); UPDATE_VAL 253 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE)); UPDATE_VAL 259 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); UPDATE_VAL 265 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN)); UPDATE_VAL 271 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO)); UPDATE_VAL 277 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO)); UPDATE_VAL 283 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST)); UPDATE_VAL 289 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET)); UPDATE_VAL 295 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO)); UPDATE_VAL 301 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU)); UPDATE_VAL 307 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS)); UPDATE_VAL 318 arch/arc/plat-hsdk/platform.c writel(UPDATE_VAL, CREG_PAE_UPDT);