UPDATE            113 arch/powerpc/kvm/emulate_loadstore.c 			if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))
UPDATE            133 arch/powerpc/kvm/emulate_loadstore.c 			if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))
UPDATE            233 arch/powerpc/kvm/emulate_loadstore.c 			if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))
UPDATE            256 arch/powerpc/kvm/emulate_loadstore.c 			if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))
UPDATE           2022 arch/powerpc/lib/sstep.c 	u = (instr >> 20) & UPDATE;
UPDATE           2027 arch/powerpc/lib/sstep.c 		u = instr & UPDATE;
UPDATE           2578 arch/powerpc/lib/sstep.c 			op->type = MKOP(LOAD, UPDATE, 8);
UPDATE           2643 arch/powerpc/lib/sstep.c 			op->type = MKOP(STORE, UPDATE, 8);
UPDATE           3020 arch/powerpc/lib/sstep.c 		if ((op->type & UPDATE) && size == sizeof(long) &&
UPDATE           3090 arch/powerpc/lib/sstep.c 	if (op->type & UPDATE)
UPDATE           3096 drivers/crypto/caam/caamalg_qi2.c 	flc = &ctx->flc[UPDATE];
UPDATE           3101 drivers/crypto/caam/caamalg_qi2.c 	dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE],
UPDATE           3554 drivers/crypto/caam/caamalg_qi2.c 		req_ctx->flc = &ctx->flc[UPDATE];
UPDATE           3555 drivers/crypto/caam/caamalg_qi2.c 		req_ctx->flc_dma = ctx->flc_dma[UPDATE];
UPDATE            548 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 			entry->offset = vma->node.start | UPDATE;
UPDATE            616 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 		entry->offset = vma->node.start | UPDATE;
UPDATE           1345 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 	return target->node.start | UPDATE;
UPDATE           1516 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 				offset = gen8_canonical_addr(offset & ~UPDATE);
UPDATE           2829 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 			if (!(exec2_list[i].offset & UPDATE))
UPDATE           2914 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 			if (!(exec2_list[i].offset & UPDATE))
UPDATE            486 drivers/net/wireless/ath/ath9k/beacon.c 	if (sc->beacon.updateslot == UPDATE) {
UPDATE           1602 drivers/net/wireless/ath/ath9k/htc_drv_main.c 			priv->beacon.updateslot = UPDATE;
UPDATE           1813 drivers/net/wireless/ath/ath9k/main.c 			sc->beacon.updateslot = UPDATE;
UPDATE             37 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x)		UPDATE(x, 6, 0)
UPDATE             39 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x)		UPDATE(x, 7, 0)
UPDATE             54 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_FB_DIV_8(x)			UPDATE((x) >> 8, 7, 7)
UPDATE             56 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PCLK_VCO_DIV_5(x)			UPDATE(x, 5, 5)
UPDATE             58 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_PRE_DIV(x)			UPDATE(x, 4, 0)
UPDATE             60 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_FB_DIV_7_0(x)			UPDATE(x, 7, 0)
UPDATE             64 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_PCLK_DIV_B(x)			UPDATE(x, 6, 5)
UPDATE             66 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_PCLK_DIV_A(x)			UPDATE(x, 4, 0)
UPDATE             69 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_PCLK_DIV_C(x)			UPDATE(x, 6, 5)
UPDATE             71 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_PCLK_DIV_D(x)			UPDATE(x, 4, 0)
UPDATE             74 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_TMDSCLK_DIV_C(x)			UPDATE(x, 5, 4)
UPDATE             76 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_TMDSCLK_DIV_A(x)			UPDATE(x, 3, 2)
UPDATE             78 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_PRE_PLL_TMDSCLK_DIV_B(x)			UPDATE(x, 1, 0)
UPDATE             82 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_POST_DIV_ENABLE			UPDATE(3, 7, 6)
UPDATE             84 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_PRE_DIV(x)			UPDATE(x, 4, 0)
UPDATE             86 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_FB_DIV_7_0(x)			UPDATE(x, 7, 0)
UPDATE             89 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_FB_DIV_8(x)			UPDATE((x) >> 8, 7, 7)
UPDATE             91 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_POST_PLL_POST_DIV(x)			UPDATE(x, 5, 4)
UPDATE             96 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_CLK_CH_TA(x)			UPDATE(x, 7, 6)
UPDATE             97 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH2_TA(x)			UPDATE(x, 5, 4)
UPDATE             98 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH1_TA(x)			UPDATE(x, 3, 2)
UPDATE             99 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH0_TA(x)			UPDATE(x, 1, 0)
UPDATE            102 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x)		UPDATE(x, 5, 4)
UPDATE            104 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x)		UPDATE(x, 3, 2)
UPDATE            106 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x)		UPDATE(x, 1, 0)
UPDATE            108 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x)		UPDATE(x, 7, 4)
UPDATE            109 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x)		UPDATE(x, 3, 0)
UPDATE            111 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x)		UPDATE(x, 7, 4)
UPDATE            112 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x)		UPDATE(x, 3, 0)
UPDATE            123 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_INT_TMDS_CLK(x)				UPDATE(x, 7, 4)
UPDATE            124 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_INT_TMDS_D2(x)				UPDATE(x, 3, 0)
UPDATE            126 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_INT_TMDS_D1(x)				UPDATE(x, 7, 4)
UPDATE            127 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_INT_TMDS_D0(x)				UPDATE(x, 3, 0)
UPDATE            135 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PCLK_VCO_DIV_5(x)			UPDATE(x, 1, 1)
UPDATE            139 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_PRE_DIV(x)			UPDATE(x, 5, 0)
UPDATE            144 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_FRAC_DIV_DISABLE			UPDATE(3, 5, 4)
UPDATE            146 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_FB_DIV_11_8(x)			UPDATE((x) >> 8, 3, 0)
UPDATE            148 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_FB_DIV_7_0(x)			UPDATE(x, 7, 0)
UPDATE            151 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_TMDSCLK_DIV_C(x)			UPDATE(x, 1, 0)
UPDATE            153 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_TMDSCLK_DIV_B(x)			UPDATE(x, 3, 2)
UPDATE            155 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_TMDSCLK_DIV_A(x)			UPDATE(x, 5, 4)
UPDATE            159 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_PCLK_DIV_B(x)			UPDATE(x, 6, 5)
UPDATE            161 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_PCLK_DIV_A(x)			UPDATE(x, 4, 0)
UPDATE            165 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_PCLK_DIV_C(x)			UPDATE(x, 6, 5)
UPDATE            167 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_PCLK_DIV_D(x)			UPDATE(x, 4, 0)
UPDATE            175 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_POST_PLL_FB_DIV_8(x)			UPDATE((x) >> 8, 7, 7)
UPDATE            176 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_POST_PLL_PRE_DIV(x)			UPDATE(x, 4, 0)
UPDATE            178 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_POST_PLL_FB_DIV_7_0(x)			UPDATE(x, 7, 0)
UPDATE            199 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x)	UPDATE((x) >> 8, 6, 0)
UPDATE            201 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x)		UPDATE(x, 7, 0)
UPDATE            203 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TERM_RESISTOR_50				UPDATE(0, 2, 1)
UPDATE            204 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TERM_RESISTOR_62_5			UPDATE(1, 2, 1)
UPDATE            205 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TERM_RESISTOR_75				UPDATE(2, 2, 1)
UPDATE            206 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_TERM_RESISTOR_100			UPDATE(3, 2, 1)
UPDATE            222 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_FRAC_DIV_23_16(x)		UPDATE((x) >> 16, 7, 0)
UPDATE            224 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_FRAC_DIV_15_8(x)			UPDATE((x) >> 8, 7, 0)
UPDATE            226 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define RK3328_PRE_PLL_FRAC_DIV_7_0(x)			UPDATE(x, 7, 0)
UPDATE            697 lib/zlib_inflate/inflate.c                         UPDATE(state->check, put - out, out);
UPDATE            739 lib/zlib_inflate/inflate.c             UPDATE(state->check, strm->next_out - out, out);
UPDATE            789 lib/zlib_inflate/inflate.c         UPDATE(state->check, z->next_in, z->avail_in);