ACC_ALL          3353 arch/x86/kvm/mmu.c 					      it.level - 1, true, ACC_ALL);
ACC_ALL          3361 arch/x86/kvm/mmu.c 	ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
ACC_ALL          3681 arch/x86/kvm/mmu.c 	if (handle_abnormal_pfn(vcpu, gpa, gfn, pfn, ACC_ALL, &r))
ACC_ALL          3789 arch/x86/kvm/mmu.c 				vcpu->arch.mmu->shadow_root_level, 1, ACC_ALL);
ACC_ALL          3804 arch/x86/kvm/mmu.c 					i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
ACC_ALL          3846 arch/x86/kvm/mmu.c 				vcpu->arch.mmu->shadow_root_level, 0, ACC_ALL);
ACC_ALL          3883 arch/x86/kvm/mmu.c 				      0, ACC_ALL);
ACC_ALL          4321 arch/x86/kvm/mmu.c 	if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
ACC_ALL          4989 arch/x86/kvm/mmu.c 	role.base.access = ACC_ALL;
ACC_ALL          5126 arch/x86/kvm/mmu.c 	role.base.access = ACC_ALL;