BLC_PWM_PCH_CTL2  540 drivers/gpu/drm/i915/display/intel_panel.c 	return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
BLC_PWM_PCH_CTL2  608 drivers/gpu/drm/i915/display/intel_panel.c 	u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
BLC_PWM_PCH_CTL2  609 drivers/gpu/drm/i915/display/intel_panel.c 	I915_WRITE(BLC_PWM_PCH_CTL2, val | level);
BLC_PWM_PCH_CTL2  906 drivers/gpu/drm/i915/display/intel_panel.c 	I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
BLC_PWM_PCH_CTL2  959 drivers/gpu/drm/i915/display/intel_panel.c 	I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
BLC_PWM_PCH_CTL2 1584 drivers/gpu/drm/i915/display/intel_panel.c 	pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
BLC_PWM_PCH_CTL2 1632 drivers/gpu/drm/i915/display/intel_panel.c 	pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
BLC_PWM_PCH_CTL2 2193 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);