BLC_PWM_PCH_CTL1 4268 drivers/gpu/drm/i915/display/intel_display_power.c 	I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
BLC_PWM_PCH_CTL1  751 drivers/gpu/drm/i915/display/intel_panel.c 	tmp = I915_READ(BLC_PWM_PCH_CTL1);
BLC_PWM_PCH_CTL1  752 drivers/gpu/drm/i915/display/intel_panel.c 	I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
BLC_PWM_PCH_CTL1  766 drivers/gpu/drm/i915/display/intel_panel.c 	tmp = I915_READ(BLC_PWM_PCH_CTL1);
BLC_PWM_PCH_CTL1  767 drivers/gpu/drm/i915/display/intel_panel.c 	I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
BLC_PWM_PCH_CTL1  882 drivers/gpu/drm/i915/display/intel_panel.c 	pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
BLC_PWM_PCH_CTL1  886 drivers/gpu/drm/i915/display/intel_panel.c 		I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
BLC_PWM_PCH_CTL1  916 drivers/gpu/drm/i915/display/intel_panel.c 	I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
BLC_PWM_PCH_CTL1  917 drivers/gpu/drm/i915/display/intel_panel.c 	POSTING_READ(BLC_PWM_PCH_CTL1);
BLC_PWM_PCH_CTL1  918 drivers/gpu/drm/i915/display/intel_panel.c 	I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
BLC_PWM_PCH_CTL1  940 drivers/gpu/drm/i915/display/intel_panel.c 	pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
BLC_PWM_PCH_CTL1  944 drivers/gpu/drm/i915/display/intel_panel.c 		I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
BLC_PWM_PCH_CTL1  965 drivers/gpu/drm/i915/display/intel_panel.c 	I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
BLC_PWM_PCH_CTL1  966 drivers/gpu/drm/i915/display/intel_panel.c 	POSTING_READ(BLC_PWM_PCH_CTL1);
BLC_PWM_PCH_CTL1  967 drivers/gpu/drm/i915/display/intel_panel.c 	I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
BLC_PWM_PCH_CTL1 1581 drivers/gpu/drm/i915/display/intel_panel.c 	pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
BLC_PWM_PCH_CTL1 1615 drivers/gpu/drm/i915/display/intel_panel.c 		I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE);
BLC_PWM_PCH_CTL1 1629 drivers/gpu/drm/i915/display/intel_panel.c 	pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
BLC_PWM_PCH_CTL1 2192 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);