BLC_PWM_CTL2 75 drivers/gpu/drm/gma500/cdv_device.c return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; BLC_PWM_CTL2 281 drivers/gpu/drm/gma500/cdv_device.c regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); BLC_PWM_CTL2 349 drivers/gpu/drm/gma500/cdv_device.c REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); BLC_PWM_CTL2 2076 drivers/gpu/drm/gma500/cdv_intel_dp.c pwm_ctrl = REG_READ(BLC_PWM_CTL2); BLC_PWM_CTL2 2078 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(BLC_PWM_CTL2, pwm_ctrl); BLC_PWM_CTL2 732 drivers/gpu/drm/gma500/cdv_intel_lvds.c pwm = REG_READ(BLC_PWM_CTL2); BLC_PWM_CTL2 738 drivers/gpu/drm/gma500/cdv_intel_lvds.c REG_WRITE(BLC_PWM_CTL2, pwm); BLC_PWM_CTL2 84 drivers/gpu/drm/gma500/oaktrail_device.c REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); BLC_PWM_CTL2 125 drivers/gpu/drm/gma500/oaktrail_device.c REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); BLC_PWM_CTL2 237 drivers/gpu/drm/gma500/oaktrail_device.c regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); BLC_PWM_CTL2 361 drivers/gpu/drm/gma500/oaktrail_device.c PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2); BLC_PWM_CTL2 782 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CTL2); BLC_PWM_CTL2 783 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); BLC_PWM_CTL2 1018 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = I915_READ(BLC_PWM_CTL2); BLC_PWM_CTL2 1022 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL2, ctl2); BLC_PWM_CTL2 1037 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL2, ctl2); BLC_PWM_CTL2 1038 drivers/gpu/drm/i915/display/intel_panel.c POSTING_READ(BLC_PWM_CTL2); BLC_PWM_CTL2 1039 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); BLC_PWM_CTL2 1700 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = I915_READ(BLC_PWM_CTL2);