BLC_PWM_CTL 80 drivers/gpu/drm/gma500/cdv_device.c u32 max = REG_READ(BLC_PWM_CTL); BLC_PWM_CTL 98 drivers/gpu/drm/gma500/cdv_device.c u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; BLC_PWM_CTL 134 drivers/gpu/drm/gma500/cdv_device.c blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; BLC_PWM_CTL 135 drivers/gpu/drm/gma500/cdv_device.c REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | BLC_PWM_CTL 280 drivers/gpu/drm/gma500/cdv_device.c regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); BLC_PWM_CTL 353 drivers/gpu/drm/gma500/cdv_device.c REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL); BLC_PWM_CTL 62 drivers/gpu/drm/gma500/cdv_intel_lvds.c retval = ((REG_READ(BLC_PWM_CTL) & BLC_PWM_CTL 132 drivers/gpu/drm/gma500/cdv_intel_lvds.c REG_WRITE(BLC_PWM_CTL, BLC_PWM_CTL 170 drivers/gpu/drm/gma500/cdv_intel_lvds.c REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; BLC_PWM_CTL 171 drivers/gpu/drm/gma500/cdv_intel_lvds.c REG_WRITE(BLC_PWM_CTL, BLC_PWM_CTL 317 drivers/gpu/drm/gma500/cdv_intel_lvds.c mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); BLC_PWM_CTL 68 drivers/gpu/drm/gma500/oaktrail_device.c max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; BLC_PWM_CTL 85 drivers/gpu/drm/gma500/oaktrail_device.c REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); BLC_PWM_CTL 126 drivers/gpu/drm/gma500/oaktrail_device.c REG_WRITE(BLC_PWM_CTL, value | (value << 16)); BLC_PWM_CTL 236 drivers/gpu/drm/gma500/oaktrail_device.c regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL); BLC_PWM_CTL 366 drivers/gpu/drm/gma500/oaktrail_device.c PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL); BLC_PWM_CTL 162 drivers/gpu/drm/gma500/oaktrail_lvds.c mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); BLC_PWM_CTL 175 drivers/gpu/drm/gma500/oaktrail_lvds.c ret = ((REG_READ(BLC_PWM_CTL) & BLC_PWM_CTL 86 drivers/gpu/drm/gma500/psb_device.c REG_WRITE(BLC_PWM_CTL, BLC_PWM_CTL 64 drivers/gpu/drm/gma500/psb_intel_lvds.c ret = REG_READ(BLC_PWM_CTL); BLC_PWM_CTL 76 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); BLC_PWM_CTL 146 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(BLC_PWM_CTL, BLC_PWM_CTL 188 drivers/gpu/drm/gma500/psb_intel_lvds.c blc_pwm_ctl = REG_READ(BLC_PWM_CTL); BLC_PWM_CTL 190 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(BLC_PWM_CTL, BLC_PWM_CTL 267 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); BLC_PWM_CTL 308 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL); BLC_PWM_CTL 433 drivers/gpu/drm/gma500/psb_intel_lvds.c mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); BLC_PWM_CTL 556 drivers/gpu/drm/i915/display/intel_panel.c val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; BLC_PWM_CTL 646 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CTL) & ~mask; BLC_PWM_CTL 647 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL, tmp | level); BLC_PWM_CTL 978 drivers/gpu/drm/i915/display/intel_panel.c ctl = I915_READ(BLC_PWM_CTL); BLC_PWM_CTL 981 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL, 0); BLC_PWM_CTL 994 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL, ctl); BLC_PWM_CTL 995 drivers/gpu/drm/i915/display/intel_panel.c POSTING_READ(BLC_PWM_CTL); BLC_PWM_CTL 1030 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL, ctl); BLC_PWM_CTL 1661 drivers/gpu/drm/i915/display/intel_panel.c ctl = I915_READ(BLC_PWM_CTL); BLC_PWM_CTL 1704 drivers/gpu/drm/i915/display/intel_panel.c ctl = I915_READ(BLC_PWM_CTL);