BLC_PWM_CPU_CTL2 4263 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, BLC_PWM_CPU_CTL2 745 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CPU_CTL2); BLC_PWM_CPU_CTL2 748 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); BLC_PWM_CPU_CTL2 763 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CPU_CTL2); BLC_PWM_CPU_CTL2 764 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); BLC_PWM_CPU_CTL2 933 drivers/gpu/drm/i915/display/intel_panel.c cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); BLC_PWM_CPU_CTL2 937 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); BLC_PWM_CPU_CTL2 951 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); BLC_PWM_CPU_CTL2 952 drivers/gpu/drm/i915/display/intel_panel.c POSTING_READ(BLC_PWM_CPU_CTL2); BLC_PWM_CPU_CTL2 953 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE); BLC_PWM_CPU_CTL2 1587 drivers/gpu/drm/i915/display/intel_panel.c cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); BLC_PWM_CPU_CTL2 1617 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 & ~BLM_PWM_ENABLE); BLC_PWM_CPU_CTL2 1648 drivers/gpu/drm/i915/display/intel_panel.c cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); BLC_PWM_CPU_CTL2 2190 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);