TXX9_IRQ_BASE 118 arch/mips/include/asm/txx9/jmr3927.h #define JMR3927_IRQ_IRC TXX9_IRQ_BASE TXX9_IRQ_BASE 70 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR) TXX9_IRQ_BASE 76 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1)) TXX9_IRQ_BASE 85 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) TXX9_IRQ_BASE 102 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_IRQ_IRC TXX9_IRQ_BASE TXX9_IRQ_BASE 103 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR) TXX9_IRQ_BASE 133 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0)) TXX9_IRQ_BASE 135 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1)) TXX9_IRQ_BASE 122 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_IRQ_IOC (TXX9_IRQ_BASE + TX4939_NUM_IR) TXX9_IRQ_BASE 126 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_IRQ_IOCINT (TXX9_IRQ_BASE + TX4939_IR_INT(0)) TXX9_IRQ_BASE 128 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_IRQ_ETHER (TXX9_IRQ_BASE + TX4939_IR_INT(1)) TXX9_IRQ_BASE 68 arch/mips/kernel/irq_txx9.c unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; TXX9_IRQ_BASE 84 arch/mips/kernel/irq_txx9.c unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; TXX9_IRQ_BASE 104 arch/mips/kernel/irq_txx9.c unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; TXX9_IRQ_BASE 114 arch/mips/kernel/irq_txx9.c unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; TXX9_IRQ_BASE 157 arch/mips/kernel/irq_txx9.c irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &txx9_irq_chip, TXX9_IRQ_BASE 189 arch/mips/kernel/irq_txx9.c return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1)); TXX9_IRQ_BASE 226 arch/mips/pci/ops-tx3927.c if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI, TXX9_IRQ_BASE 86 arch/mips/pci/pci-tx4927.c if (request_irq(TXX9_IRQ_BASE + TX4927_IR_PCIERR, TXX9_IRQ_BASE 122 arch/mips/pci/pci-tx4938.c return TXX9_IRQ_BASE + TX4938_IR_ETH0; TXX9_IRQ_BASE 127 arch/mips/pci/pci-tx4938.c return TXX9_IRQ_BASE + TX4938_IR_ETH1; TXX9_IRQ_BASE 137 arch/mips/pci/pci-tx4938.c if (request_irq(TXX9_IRQ_BASE + TX4938_IR_PCIERR, TXX9_IRQ_BASE 58 arch/mips/pci/pci-tx4939.c return TXX9_IRQ_BASE + TX4939_IR_ETH(0); TXX9_IRQ_BASE 63 arch/mips/pci/pci-tx4939.c return TXX9_IRQ_BASE + TX4939_IR_ETH(1); TXX9_IRQ_BASE 85 arch/mips/pci/pci-tx4939.c irq = TXX9_IRQ_BASE + TX4939_IR_INTA; TXX9_IRQ_BASE 88 arch/mips/pci/pci-tx4939.c irq = TXX9_IRQ_BASE + TX4939_IR_INTB; TXX9_IRQ_BASE 91 arch/mips/pci/pci-tx4939.c irq = TXX9_IRQ_BASE + TX4939_IR_INTC; TXX9_IRQ_BASE 94 arch/mips/pci/pci-tx4939.c irq = TXX9_IRQ_BASE + TX4939_IR_INTD; TXX9_IRQ_BASE 102 arch/mips/pci/pci-tx4939.c if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR, TXX9_IRQ_BASE 55 arch/mips/txx9/generic/irq_tx4939.c unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; TXX9_IRQ_BASE 73 arch/mips/txx9/generic/irq_tx4939.c unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; TXX9_IRQ_BASE 92 arch/mips/txx9/generic/irq_tx4939.c unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; TXX9_IRQ_BASE 106 arch/mips/txx9/generic/irq_tx4939.c unsigned int irq_nr = d->irq - TXX9_IRQ_BASE; TXX9_IRQ_BASE 179 arch/mips/txx9/generic/irq_tx4939.c irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip, TXX9_IRQ_BASE 214 arch/mips/txx9/generic/irq_tx4939.c return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1)); TXX9_IRQ_BASE 110 arch/mips/txx9/generic/setup_tx3927.c TXX9_IRQ_BASE + TX3927_IR_TMR(evt_tmrnr), TXX9_IRQ_BASE 121 arch/mips/txx9/generic/setup_tx3927.c TXX9_IRQ_BASE + TX3927_IR_SIO(i), TXX9_IRQ_BASE 227 arch/mips/txx9/generic/setup_tx4927.c TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr), TXX9_IRQ_BASE 237 arch/mips/txx9/generic/setup_tx4927.c TXX9_IRQ_BASE + TX4927_IR_SIO(i), TXX9_IRQ_BASE 262 arch/mips/txx9/generic/setup_tx4927.c TXX9_IRQ_BASE + TX4927_IR_DMA(0), &plat_data); TXX9_IRQ_BASE 304 arch/mips/txx9/generic/setup_tx4927.c TXX9_IRQ_BASE + TX4927_IR_ACLC, TXX9_IRQ_BASE 284 arch/mips/txx9/generic/setup_tx4938.c TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr), TXX9_IRQ_BASE 299 arch/mips/txx9/generic/setup_tx4938.c TXX9_IRQ_BASE + TX4938_IR_SIO(i), TXX9_IRQ_BASE 307 arch/mips/txx9/generic/setup_tx4938.c TXX9_IRQ_BASE + TX4938_IR_SPI); TXX9_IRQ_BASE 315 arch/mips/txx9/generic/setup_tx4938.c txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0); TXX9_IRQ_BASE 317 arch/mips/txx9/generic/setup_tx4938.c txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1); TXX9_IRQ_BASE 409 arch/mips/txx9/generic/setup_tx4938.c TXX9_IRQ_BASE + TX4938_IR_DMA(i, 0), TXX9_IRQ_BASE 421 arch/mips/txx9/generic/setup_tx4938.c TXX9_IRQ_BASE + TX4938_IR_ACLC, TXX9_IRQ_BASE 294 arch/mips/txx9/generic/setup_tx4939.c TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr), TXX9_IRQ_BASE 315 arch/mips/txx9/generic/setup_tx4939.c TXX9_IRQ_BASE + TX4939_IR_SIO(i), TXX9_IRQ_BASE 339 arch/mips/txx9/generic/setup_tx4939.c if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0)) TXX9_IRQ_BASE 341 arch/mips/txx9/generic/setup_tx4939.c else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1)) TXX9_IRQ_BASE 363 arch/mips/txx9/generic/setup_tx4939.c txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0); TXX9_IRQ_BASE 365 arch/mips/txx9/generic/setup_tx4939.c txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1); TXX9_IRQ_BASE 396 arch/mips/txx9/generic/setup_tx4939.c .start = TXX9_IRQ_BASE + TX4939_IR_ATA(0), TXX9_IRQ_BASE 406 arch/mips/txx9/generic/setup_tx4939.c .start = TXX9_IRQ_BASE + TX4939_IR_ATA(1), TXX9_IRQ_BASE 440 arch/mips/txx9/generic/setup_tx4939.c .start = TXX9_IRQ_BASE + TX4939_IR_RTC, TXX9_IRQ_BASE 480 arch/mips/txx9/generic/setup_tx4939.c TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0), TXX9_IRQ_BASE 491 arch/mips/txx9/generic/setup_tx4939.c TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1);