TV_CTL 910 drivers/gpu/drm/i915/display/intel_tv.c u32 tmp = I915_READ(TV_CTL); TV_CTL 929 drivers/gpu/drm/i915/display/intel_tv.c I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); TV_CTL 940 drivers/gpu/drm/i915/display/intel_tv.c I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); TV_CTL 1099 drivers/gpu/drm/i915/display/intel_tv.c tv_ctl = I915_READ(TV_CTL); TV_CTL 1438 drivers/gpu/drm/i915/display/intel_tv.c tv_ctl = I915_READ(TV_CTL); TV_CTL 1561 drivers/gpu/drm/i915/display/intel_tv.c I915_WRITE(TV_CTL, tv_ctl); TV_CTL 1586 drivers/gpu/drm/i915/display/intel_tv.c save_tv_ctl = tv_ctl = I915_READ(TV_CTL); TV_CTL 1612 drivers/gpu/drm/i915/display/intel_tv.c I915_WRITE(TV_CTL, tv_ctl); TV_CTL 1642 drivers/gpu/drm/i915/display/intel_tv.c I915_WRITE(TV_CTL, save_tv_ctl); TV_CTL 1643 drivers/gpu/drm/i915/display/intel_tv.c POSTING_READ(TV_CTL); TV_CTL 1874 drivers/gpu/drm/i915/display/intel_tv.c if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)